Lines Matching refs:Fixups
45 SmallVectorImpl<MCFixup> &Fixups, in getDirectBrEncoding() argument
48 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDirectBrEncoding()
51 Fixups.push_back(MCFixup::create(0, MO.getExpr(), in getDirectBrEncoding()
57 SmallVectorImpl<MCFixup> &Fixups, in getCondBrEncoding() argument
60 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding()
63 Fixups.push_back(MCFixup::create(0, MO.getExpr(), in getCondBrEncoding()
70 SmallVectorImpl<MCFixup> &Fixups, in getAbsDirectBrEncoding() argument
73 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding()
76 Fixups.push_back(MCFixup::create(0, MO.getExpr(), in getAbsDirectBrEncoding()
83 SmallVectorImpl<MCFixup> &Fixups, in getAbsCondBrEncoding() argument
86 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding()
89 Fixups.push_back(MCFixup::create(0, MO.getExpr(), in getAbsCondBrEncoding()
95 SmallVectorImpl<MCFixup> &Fixups, in getImm16Encoding() argument
98 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getImm16Encoding()
101 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), in getImm16Encoding()
107 SmallVectorImpl<MCFixup> &Fixups, in getMemRIEncoding() argument
112 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16; in getMemRIEncoding()
116 return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits; in getMemRIEncoding()
119 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), in getMemRIEncoding()
125 SmallVectorImpl<MCFixup> &Fixups, in getMemRIXEncoding() argument
130 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14; in getMemRIXEncoding()
134 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits; in getMemRIXEncoding()
137 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), in getMemRIXEncoding()
143 SmallVectorImpl<MCFixup> &Fixups, in getMemRIX16Encoding() argument
148 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12; in getMemRIX16Encoding()
154 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits; in getMemRIX16Encoding()
158 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), in getMemRIX16Encoding()
164 SmallVectorImpl<MCFixup> &Fixups, in getSPE8DisEncoding() argument
170 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; in getSPE8DisEncoding()
174 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3; in getSPE8DisEncoding()
179 SmallVectorImpl<MCFixup> &Fixups, in getSPE4DisEncoding() argument
185 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; in getSPE4DisEncoding()
189 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2; in getSPE4DisEncoding()
194 SmallVectorImpl<MCFixup> &Fixups, in getSPE2DisEncoding() argument
200 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; in getSPE2DisEncoding()
204 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1; in getSPE2DisEncoding()
209 SmallVectorImpl<MCFixup> &Fixups, in getTLSRegEncoding() argument
212 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI); in getTLSRegEncoding()
217 Fixups.push_back(MCFixup::create(0, MO.getExpr(), in getTLSRegEncoding()
225 SmallVectorImpl<MCFixup> &Fixups, in getTLSCallEncoding() argument
231 Fixups.push_back(MCFixup::create(0, MO.getExpr(), in getTLSCallEncoding()
233 return getDirectBrEncoding(MI, OpNo, Fixups, STI); in getTLSCallEncoding()
238 SmallVectorImpl<MCFixup> &Fixups, in get_crbitm_encoding() argument
263 SmallVectorImpl<MCFixup> &Fixups, in getMachineOpValue() argument
284 const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, in encodeInstruction() argument
289 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); in encodeInstruction()