Lines Matching refs:SDValue

77 bool MipsDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,  in selectAddrRegImm()
78 SDValue &Offset) const { in selectAddrRegImm()
83 bool MipsDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base, in selectAddrDefault()
84 SDValue &Offset) const { in selectAddrDefault()
89 bool MipsDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base, in selectIntAddr()
90 SDValue &Offset) const { in selectIntAddr()
95 bool MipsDAGToDAGISel::selectIntAddr11MM(SDValue Addr, SDValue &Base, in selectIntAddr11MM()
96 SDValue &Offset) const { in selectIntAddr11MM()
101 bool MipsDAGToDAGISel::selectIntAddr12MM(SDValue Addr, SDValue &Base, in selectIntAddr12MM()
102 SDValue &Offset) const { in selectIntAddr12MM()
107 bool MipsDAGToDAGISel::selectIntAddr16MM(SDValue Addr, SDValue &Base, in selectIntAddr16MM()
108 SDValue &Offset) const { in selectIntAddr16MM()
113 bool MipsDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base, in selectIntAddrLSL2MM()
114 SDValue &Offset) const { in selectIntAddrLSL2MM()
119 bool MipsDAGToDAGISel::selectIntAddrSImm10(SDValue Addr, SDValue &Base, in selectIntAddrSImm10()
120 SDValue &Offset) const { in selectIntAddrSImm10()
125 bool MipsDAGToDAGISel::selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base, in selectIntAddrSImm10Lsl1()
126 SDValue &Offset) const { in selectIntAddrSImm10Lsl1()
131 bool MipsDAGToDAGISel::selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base, in selectIntAddrSImm10Lsl2()
132 SDValue &Offset) const { in selectIntAddrSImm10Lsl2()
137 bool MipsDAGToDAGISel::selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base, in selectIntAddrSImm10Lsl3()
138 SDValue &Offset) const { in selectIntAddrSImm10Lsl3()
143 bool MipsDAGToDAGISel::selectAddr16(SDValue Addr, SDValue &Base, in selectAddr16()
144 SDValue &Offset) { in selectAddr16()
149 bool MipsDAGToDAGISel::selectAddr16SP(SDValue Addr, SDValue &Base, in selectAddr16SP()
150 SDValue &Offset) { in selectAddr16SP()
161 bool MipsDAGToDAGISel::selectVSplatUimm1(SDValue N, SDValue &Imm) const { in selectVSplatUimm1()
166 bool MipsDAGToDAGISel::selectVSplatUimm2(SDValue N, SDValue &Imm) const { in selectVSplatUimm2()
171 bool MipsDAGToDAGISel::selectVSplatUimm3(SDValue N, SDValue &Imm) const { in selectVSplatUimm3()
176 bool MipsDAGToDAGISel::selectVSplatUimm4(SDValue N, SDValue &Imm) const { in selectVSplatUimm4()
181 bool MipsDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &Imm) const { in selectVSplatUimm5()
186 bool MipsDAGToDAGISel::selectVSplatUimm6(SDValue N, SDValue &Imm) const { in selectVSplatUimm6()
191 bool MipsDAGToDAGISel::selectVSplatUimm8(SDValue N, SDValue &Imm) const { in selectVSplatUimm8()
196 bool MipsDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &Imm) const { in selectVSplatSimm5()
201 bool MipsDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const { in selectVSplatUimmPow2()
206 bool MipsDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N, SDValue &Imm) const { in selectVSplatUimmInvPow2()
211 bool MipsDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const { in selectVSplatMaskL()
216 bool MipsDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const { in selectVSplatMaskR()
261 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, in SelectInlineAsmMemoryOperand()
262 std::vector<SDValue> &OutOps) { in SelectInlineAsmMemoryOperand()