156       MachineInstr &MI2 = *SI.getSUnit()->getInstr();  in apply()
163         for (SDep &PI : SI.getSUnit()->Preds) {  in apply()
164           if (PI.getSUnit() != &SU || PI.getKind() != SDep::Order)  in apply()
167           SI.getSUnit()->setDepthDirty();  in apply()
350     MachineInstr *DDst = Dst->Succs[0].getSUnit()->getInstr();  in adjustSchedDependency()
423     if (!I.isAssignedRegDep() || I.getSUnit() != Dst)  in restoreLatency()
462     if (!I.isAssignedRegDep() || I.getSUnit() != Dst)  in changeLatency()
479         !I.getSUnit()->getInstr()->isPseudo())  in getZeroLatency()
480       return I.getSUnit();  in getZeroLatency()
557       if (ExclSrc.count(I.getSUnit()) == 0 &&  in isBestZeroLatency()
558           isBestZeroLatency(I.getSUnit(), DstBest, TII, ExclSrc, ExclDst))  in isBestZeroLatency()
559         changeLatency(I.getSUnit(), DstBest, 0);  in isBestZeroLatency()
565       if (ExclDst.count(I.getSUnit()) == 0 &&  in isBestZeroLatency()
566           isBestZeroLatency(SrcBest, I.getSUnit(), TII, ExclSrc, ExclDst))  in isBestZeroLatency()
567         changeLatency(SrcBest, I.getSUnit(), 0);  in isBestZeroLatency()