654              .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())  in splitMemRef()
657               .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())  in splitMemRef()
663              .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())  in splitMemRef()
667               .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())  in splitMemRef()
772     .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg());  in splitExt()
812       .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
837         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
840         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
843         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)  in splitShift()
849         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)  in splitShift()
860         .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR)  in splitShift()
871       .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR));  in splitShift()
883         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
886         .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR);  in splitShift()
889         .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR))  in splitShift()
947       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)  in splitAslOr()
948       .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR);  in splitAslOr()
954       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)  in splitAslOr()
955       .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)  in splitAslOr()
959       .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)  in splitAslOr()
976       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);  in splitAslOr()
987       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);  in splitAslOr()