Lines Matching refs:RegisterCell
203 static bool isEqual(const BitTracker::RegisterCell &RC1, uint16_t B1,
204 const BitTracker::RegisterCell &RC2, uint16_t B2, uint16_t W);
205 static bool isZero(const BitTracker::RegisterCell &RC, uint16_t B,
207 static bool getConst(const BitTracker::RegisterCell &RC, uint16_t B,
314 bool HexagonBitSimplify::isEqual(const BitTracker::RegisterCell &RC1, in isEqual()
315 uint16_t B1, const BitTracker::RegisterCell &RC2, uint16_t B2, in isEqual()
330 bool HexagonBitSimplify::isZero(const BitTracker::RegisterCell &RC, in isZero()
339 bool HexagonBitSimplify::getConst(const BitTracker::RegisterCell &RC, in getConst()
1282 const BitTracker::RegisterCell &DC = BT.lookup(RD.Reg); in usedBitsEqual()
1283 const BitTracker::RegisterCell &SC = BT.lookup(RS.Reg); in usedBitsEqual()
1325 const BitTracker::RegisterCell &DC = BT.lookup(RD.Reg); in processBlock()
1342 const BitTracker::RegisterCell &SC = BT.lookup(RS.Reg); in processBlock()
1477 const BitTracker::RegisterCell &DRC = BT.lookup(DR); in processBlock()
1543 const BitTracker::RegisterCell &InpRC = BT.lookup(Inp.Reg); in findMatch()
1552 const BitTracker::RegisterCell &RC = BT.lookup(R); in findMatch()
1756 bool matchHalf(unsigned SelfR, const BitTracker::RegisterCell &RC,
1760 bool matchPackhl(unsigned SelfR, const BitTracker::RegisterCell &RC,
1767 const BitTracker::RegisterCell &RC);
1769 const BitTracker::RegisterCell &RC);
1771 const BitTracker::RegisterCell &RC);
1773 const BitTracker::RegisterCell &RC);
1775 const BitTracker::RegisterCell &RC, const RegisterSet &AVs);
1777 const BitTracker::RegisterCell &RC);
1779 const BitTracker::RegisterCell &RC, const RegisterSet &AVs);
1800 const BitTracker::RegisterCell &RC, unsigned B, RegHalf &RH) { in matchHalf()
1828 const BitTracker::RegisterCell &SC = BT.lookup(Reg); in matchHalf()
1887 const BitTracker::RegisterCell &RC, BitTracker::RegisterRef &Rs, in matchPackhl()
1926 const BitTracker::RegisterCell &RC = BT.lookup(RS.Reg); in genStoreUpperHalf()
1971 const BitTracker::RegisterCell &RC = BT.lookup(RS.Reg); in genStoreImmediate()
2017 BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC) { in genPackhl()
2044 BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC) { in genExtractHalf()
2083 BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC) { in genCombineHalf()
2115 BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC) { in genExtractLow()
2149 const BitTracker::RegisterCell &SC = BT.lookup(RS.Reg); in genExtractLow()
2175 BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC, in genBitSplit()
2195 auto ctlz = [] (const BitTracker::RegisterCell &C) -> unsigned { in genBitSplit()
2236 const BitTracker::RegisterCell &SC = BT.lookup(S); in genBitSplit()
2328 BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC) { in simplifyTstbit()
2343 const BitTracker::RegisterCell &SC = BT.lookup(RS.Reg); in simplifyTstbit()
2388 BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC, in simplifyExtractLow()
2475 const BitTracker::RegisterCell &SC = BT.lookup(R); in simplifyExtractLow()
2603 const BitTracker::RegisterCell &SC = BT.lookup(SR.Reg); in simplifyRCmp0()
2621 BitTracker::RegisterCell NewRC(W); in simplifyRCmp0()
2689 BitTracker::RegisterCell NewRC(W); in simplifyRCmp0()
2733 const BitTracker::RegisterCell &RC = BT.lookup(RD.Reg); in processBlock()
2973 const BitTracker::RegisterCell &RC = BTP->lookup(Reg); in isConst()
3027 const BitTracker::RegisterCell &OutC = BTP->lookup(OutR); in isShuffleOf()
3042 const BitTracker::RegisterCell &OutC1 = BTP->lookup(OutR1); in isSameShuffle()
3043 const BitTracker::RegisterCell &OutC2 = BTP->lookup(OutR2); in isSameShuffle()