Lines Matching refs:AVR
39 addRegisterClass(MVT::i8, &AVR::GPR8RegClass); in AVRTargetLowering()
40 addRegisterClass(MVT::i16, &AVR::DREGSRegClass); in AVRTargetLowering()
48 setStackPointerRegisterToSaveRestore(AVR::SP); in AVRTargetLowering()
756 if (isa<PointerType>(Ty) && AS == AVR::ProgramMemory) { in isLegalAddressingMode()
786 if (AVR::isProgramMemoryAccess(LD)) { in getPreIndexedAddressParts()
792 if (AVR::isProgramMemoryAccess(ST)) { in getPreIndexedAddressParts()
843 if (AVR::isProgramMemoryAccess(ST)) { in getPostIndexedAddressParts()
940 static const MCPhysReg RegList8[] = {AVR::R24, AVR::R22, AVR::R20, in analyzeStandardArguments()
941 AVR::R18, AVR::R16, AVR::R14, in analyzeStandardArguments()
942 AVR::R12, AVR::R10, AVR::R8}; in analyzeStandardArguments()
943 static const MCPhysReg RegList16[] = {AVR::R25R24, AVR::R23R22, AVR::R21R20, in analyzeStandardArguments()
944 AVR::R19R18, AVR::R17R16, AVR::R15R14, in analyzeStandardArguments()
945 AVR::R13R12, AVR::R11R10, AVR::R9R8}; in analyzeStandardArguments()
1074 RC = &AVR::GPR8RegClass; in LowerFormalArguments()
1076 RC = &AVR::DREGSRegClass; in LowerFormalArguments()
1250 DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())), in LowerCall()
1452 case AVR::Lsl8: in insertShift()
1453 Opc = AVR::ADDRdRr; // LSL is an alias of ADD Rd, Rd in insertShift()
1454 RC = &AVR::GPR8RegClass; in insertShift()
1457 case AVR::Lsl16: in insertShift()
1458 Opc = AVR::LSLWRd; in insertShift()
1459 RC = &AVR::DREGSRegClass; in insertShift()
1461 case AVR::Asr8: in insertShift()
1462 Opc = AVR::ASRRd; in insertShift()
1463 RC = &AVR::GPR8RegClass; in insertShift()
1465 case AVR::Asr16: in insertShift()
1466 Opc = AVR::ASRWRd; in insertShift()
1467 RC = &AVR::DREGSRegClass; in insertShift()
1469 case AVR::Lsr8: in insertShift()
1470 Opc = AVR::LSRRd; in insertShift()
1471 RC = &AVR::GPR8RegClass; in insertShift()
1473 case AVR::Lsr16: in insertShift()
1474 Opc = AVR::LSRWRd; in insertShift()
1475 RC = &AVR::DREGSRegClass; in insertShift()
1477 case AVR::Rol8: in insertShift()
1478 Opc = AVR::ADCRdRr; // ROL is an alias of ADC Rd, Rd in insertShift()
1479 RC = &AVR::GPR8RegClass; in insertShift()
1482 case AVR::Rol16: in insertShift()
1483 Opc = AVR::ROLWRd; in insertShift()
1484 RC = &AVR::DREGSRegClass; in insertShift()
1486 case AVR::Ror8: in insertShift()
1487 Opc = AVR::RORRd; in insertShift()
1488 RC = &AVR::GPR8RegClass; in insertShift()
1490 case AVR::Ror16: in insertShift()
1491 Opc = AVR::RORWRd; in insertShift()
1492 RC = &AVR::DREGSRegClass; in insertShift()
1521 unsigned ShiftAmtReg = RI.createVirtualRegister(&AVR::LD8RegClass); in insertShift()
1522 unsigned ShiftAmtReg2 = RI.createVirtualRegister(&AVR::LD8RegClass); in insertShift()
1532 BuildMI(BB, dl, TII.get(AVR::CPIRdK)).addReg(ShiftAmtSrcReg).addImm(0); in insertShift()
1533 BuildMI(BB, dl, TII.get(AVR::BREQk)).addMBB(RemBB); in insertShift()
1540 BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftReg) in insertShift()
1545 BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftAmtReg) in insertShift()
1555 BuildMI(LoopBB, dl, TII.get(AVR::SUBIRdK), ShiftAmtReg2) in insertShift()
1558 BuildMI(LoopBB, dl, TII.get(AVR::BRNEk)).addMBB(LoopBB); in insertShift()
1562 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(AVR::PHI), DstReg) in insertShift()
1573 if (I->getOpcode() == AVR::COPY) { in isCopyMulResult()
1575 return (SrcReg == AVR::R0 || SrcReg == AVR::R1); in isCopyMulResult()
1594 BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1) in insertMul()
1595 .addReg(AVR::R1) in insertMul()
1596 .addReg(AVR::R1); in insertMul()
1608 case AVR::Lsl8: in EmitInstrWithCustomInserter()
1609 case AVR::Lsl16: in EmitInstrWithCustomInserter()
1610 case AVR::Lsr8: in EmitInstrWithCustomInserter()
1611 case AVR::Lsr16: in EmitInstrWithCustomInserter()
1612 case AVR::Rol8: in EmitInstrWithCustomInserter()
1613 case AVR::Rol16: in EmitInstrWithCustomInserter()
1614 case AVR::Ror8: in EmitInstrWithCustomInserter()
1615 case AVR::Ror16: in EmitInstrWithCustomInserter()
1616 case AVR::Asr8: in EmitInstrWithCustomInserter()
1617 case AVR::Asr16: in EmitInstrWithCustomInserter()
1619 case AVR::MULRdRr: in EmitInstrWithCustomInserter()
1620 case AVR::MULSRdRr: in EmitInstrWithCustomInserter()
1624 assert((Opc == AVR::Select16 || Opc == AVR::Select8) && in EmitInstrWithCustomInserter()
1659 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB); in EmitInstrWithCustomInserter()
1664 BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB); in EmitInstrWithCustomInserter()
1668 BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI), MI.getOperand(0).getReg()) in EmitInstrWithCustomInserter()
1858 return std::make_pair(0U, &AVR::LD8loRegClass); in getRegForInlineAsmConstraint()
1860 return std::make_pair(0U, &AVR::PTRDISPREGSRegClass); in getRegForInlineAsmConstraint()
1862 return std::make_pair(0U, &AVR::LD8RegClass); in getRegForInlineAsmConstraint()
1864 return std::make_pair(0U, &AVR::GPR8loRegClass); in getRegForInlineAsmConstraint()
1866 return std::make_pair(0U, &AVR::PTRREGSRegClass); in getRegForInlineAsmConstraint()
1868 return std::make_pair(0U, &AVR::GPRSPRegClass); in getRegForInlineAsmConstraint()
1871 return std::make_pair(0U, &AVR::GPR8RegClass); in getRegForInlineAsmConstraint()
1874 return std::make_pair(0U, &AVR::DREGSRegClass); in getRegForInlineAsmConstraint()
1876 return std::make_pair(unsigned(AVR::R0), &AVR::GPR8RegClass); in getRegForInlineAsmConstraint()
1878 return std::make_pair(0U, &AVR::IWREGSRegClass); in getRegForInlineAsmConstraint()
1881 return std::make_pair(unsigned(AVR::R27R26), &AVR::PTRREGSRegClass); in getRegForInlineAsmConstraint()
1884 return std::make_pair(unsigned(AVR::R29R28), &AVR::PTRREGSRegClass); in getRegForInlineAsmConstraint()
1887 return std::make_pair(unsigned(AVR::R31R30), &AVR::PTRREGSRegClass); in getRegForInlineAsmConstraint()
2011 .Case("r0", AVR::R0).Case("r1", AVR::R1).Case("r2", AVR::R2) in getRegisterByName()
2012 .Case("r3", AVR::R3).Case("r4", AVR::R4).Case("r5", AVR::R5) in getRegisterByName()
2013 .Case("r6", AVR::R6).Case("r7", AVR::R7).Case("r8", AVR::R8) in getRegisterByName()
2014 .Case("r9", AVR::R9).Case("r10", AVR::R10).Case("r11", AVR::R11) in getRegisterByName()
2015 .Case("r12", AVR::R12).Case("r13", AVR::R13).Case("r14", AVR::R14) in getRegisterByName()
2016 .Case("r15", AVR::R15).Case("r16", AVR::R16).Case("r17", AVR::R17) in getRegisterByName()
2017 .Case("r18", AVR::R18).Case("r19", AVR::R19).Case("r20", AVR::R20) in getRegisterByName()
2018 .Case("r21", AVR::R21).Case("r22", AVR::R22).Case("r23", AVR::R23) in getRegisterByName()
2019 .Case("r24", AVR::R24).Case("r25", AVR::R25).Case("r26", AVR::R26) in getRegisterByName()
2020 .Case("r27", AVR::R27).Case("r28", AVR::R28).Case("r29", AVR::R29) in getRegisterByName()
2021 .Case("r30", AVR::R30).Case("r31", AVR::R31) in getRegisterByName()
2022 .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30) in getRegisterByName()
2026 .Case("r0", AVR::R1R0).Case("r2", AVR::R3R2) in getRegisterByName()
2027 .Case("r4", AVR::R5R4).Case("r6", AVR::R7R6) in getRegisterByName()
2028 .Case("r8", AVR::R9R8).Case("r10", AVR::R11R10) in getRegisterByName()
2029 .Case("r12", AVR::R13R12).Case("r14", AVR::R15R14) in getRegisterByName()
2030 .Case("r16", AVR::R17R16).Case("r18", AVR::R19R18) in getRegisterByName()
2031 .Case("r20", AVR::R21R20).Case("r22", AVR::R23R22) in getRegisterByName()
2032 .Case("r24", AVR::R25R24).Case("r26", AVR::R27R26) in getRegisterByName()
2033 .Case("r28", AVR::R29R28).Case("r30", AVR::R31R30) in getRegisterByName()
2034 .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30) in getRegisterByName()