Lines Matching refs:ShiftReg
774 unsigned ShiftReg; member
1193 RegShiftedReg.ShiftReg); in isRegShiftedReg()
2062 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); in addRegShiftedRegOperands()
2969 unsigned ShiftReg, unsigned ShiftImm, SMLoc S, in CreateShiftedRegister() argument
2974 Op->RegShiftedReg.ShiftReg = ShiftReg; in CreateShiftedRegister()
3305 << RegName(RegShiftedReg.ShiftReg) << ">"; in print()
3472 int ShiftReg = 0; in tryParseShiftRegister() local
3477 ShiftReg = SrcReg; in tryParseShiftRegister()
3512 ShiftReg = tryParseRegister(); in tryParseShiftRegister()
3513 if (ShiftReg == -1) { in tryParseShiftRegister()
3524 if (ShiftReg && ShiftTy != ARM_AM::rrx) in tryParseShiftRegister()
3526 ShiftReg, Imm, in tryParseShiftRegister()