726     unsigned RegNum;  member
731     unsigned RegNum;  member
760     unsigned RegNum;  member
860     return Reg.RegNum;  in getReg()
1240            ARMMCRegisterClasses[ARM::GPRRegClassID].contains(PostIdxReg.RegNum);  in isPostIdxRegShifted()
1637               .contains(VectorList.RegNum));  in isVecListDPair()
1654               .contains(VectorList.RegNum));  in isVecListDPairSpaced()
1683               .contains(VectorList.RegNum));  in isVecListDPairAllLanes()
2018     unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;  in addCondCodeOperands()  local
2019     Inst.addOperand(MCOperand::createReg(RegNum));  in addCondCodeOperands()
2461       Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));  in addAM3OffsetOperands()
2687     Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));  in addPostIdxRegOperands()
2693     Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));  in addPostIdxRegShiftedOperands()
2719     Inst.addOperand(MCOperand::createReg(VectorList.RegNum));  in addVecListOperands()
2724     Inst.addOperand(MCOperand::createReg(VectorList.RegNum));  in addVecListIndexedOperands()
2941   static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {  in CreateCCOut()  argument
2943     Op->Reg.RegNum = RegNum;  in CreateCCOut()
2958   static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,  in CreateReg()  argument
2961     Op->Reg.RegNum = RegNum;  in CreateReg()
3065   static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,  in CreateVectorList()  argument
3070     Op->VectorList.RegNum = RegNum;  in CreateVectorList()
3079   CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,  in CreateVectorListAllLanes()  argument
3082     Op->VectorList.RegNum = RegNum;  in CreateVectorListAllLanes()
3091   CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,  in CreateVectorListIndexed()  argument
3094     Op->VectorList.RegNum = RegNum;  in CreateVectorListIndexed()
3141   CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,  in CreatePostIdxReg()  argument
3144     Op->PostIdxReg.RegNum = RegNum;  in CreatePostIdxReg()
3280        << RegName(PostIdxReg.RegNum);  in print()
3343        << RegName(VectorList.RegNum) << ">";  in print()
3347        << RegName(VectorList.RegNum) << ">";  in print()
3351        << VectorList.Count << " * " << RegName(VectorList.RegNum) << ">";  in print()
3388   unsigned RegNum = MatchRegisterName(lowerCase);  in tryParseRegister()  local
3389   if (!RegNum) {  in tryParseRegister()
3390     RegNum = StringSwitch<unsigned>(lowerCase)  in tryParseRegister()
3413   if (!RegNum) {  in tryParseRegister()
3426   if (hasD16() && RegNum >= ARM::D16 && RegNum <= ARM::D31)  in tryParseRegister()
3431   return RegNum;  in tryParseRegister()