Lines Matching refs:Operands
378 bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
380 bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
432 OperandVector &Operands);
562 bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
563 bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
565 void fixupGNULDRDAlias(StringRef Mnemonic, OperandVector &Operands);
566 bool validateLDRDSTRD(MCInst &Inst, const OperandVector &Operands,
606 SMLoc NameLoc, OperandVector &Operands) override;
614 OperandVector &Operands, MCStreamer &Out,
617 unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst,
631 SMLoc IDLoc, OperandVector &Operands);
633 OperandVector &Operands);
3439 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) { in tryParseShiftRegister() argument
3465 (ARMOperand *)Operands.pop_back_val().release()); in tryParseShiftRegister()
3525 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, in tryParseShiftRegister()
3529 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, in tryParseShiftRegister()
3541 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) { in tryParseRegisterWithWriteBack() argument
3549 Operands.push_back(ARMOperand::CreateReg(RegNo, RegStartLoc, RegEndLoc)); in tryParseRegisterWithWriteBack()
3553 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), in tryParseRegisterWithWriteBack()
3579 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), in tryParseRegisterWithWriteBack()
3638 ARMAsmParser::parseITCondCode(OperandVector &Operands) { in parseITCondCode() argument
3649 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); in parseITCondCode()
3658 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) { in parseCoprocNumOperand() argument
3673 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); in parseCoprocNumOperand()
3681 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) { in parseCoprocRegOperand() argument
3693 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); in parseCoprocRegOperand()
3700 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) { in parseCoprocOptionOperand() argument
3728 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); in parseCoprocOptionOperand()
3755 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) { in parseRegisterList() argument
3874 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); in parseRegisterList()
3878 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); in parseRegisterList()
3939 ARMAsmParser::parseVectorList(OperandVector &Operands) { in parseVectorList() argument
3958 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); in parseVectorList()
3961 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, in parseVectorList()
3965 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, in parseVectorList()
3981 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); in parseVectorList()
3986 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, in parseVectorList()
3990 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, in parseVectorList()
4162 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, in parseVectorList()
4174 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, in parseVectorList()
4179 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, in parseVectorList()
4190 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) { in parseMemBarrierOptOperand() argument
4256 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); in parseMemBarrierOptOperand()
4261 ARMAsmParser::parseTraceSyncBarrierOptOperand(OperandVector &Operands) { in parseTraceSyncBarrierOptOperand() argument
4274 Operands.push_back(ARMOperand::CreateTraceSyncBarrierOpt(ARM_TSB::CSYNC, S)); in parseTraceSyncBarrierOptOperand()
4280 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) { in parseInstSyncBarrierOptOperand() argument
4324 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt( in parseInstSyncBarrierOptOperand()
4332 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) { in parseProcIFlagsOperand() argument
4361 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); in parseProcIFlagsOperand()
4367 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) { in parseMSRMaskOperand() argument
4379 Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S)); in parseMSRMaskOperand()
4395 Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S)); in parseMSRMaskOperand()
4458 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); in parseMSRMaskOperand()
4465 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) { in parseBankedRegOperand() argument
4479 Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S)); in parseBankedRegOperand()
4484 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low, in parsePKHImm() argument
4527 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc)); in parsePKHImm()
4533 ARMAsmParser::parseSetEndImm(OperandVector &Operands) { in parseSetEndImm() argument
4551 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val, in parseSetEndImm()
4563 ARMAsmParser::parseShifterImm(OperandVector &Operands) { in parseShifterImm() argument
4625 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc)); in parseShifterImm()
4634 ARMAsmParser::parseRotImm(OperandVector &Operands) { in parseRotImm() argument
4675 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc)); in parseRotImm()
4681 ARMAsmParser::parseModImm(OperandVector &Operands) { in parseModImm() argument
4728 Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF), in parseModImm()
4741 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1)); in parseModImm()
4747 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1)); in parseModImm()
4786 Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2)); in parseModImm()
4798 ARMAsmParser::parseBitfield(OperandVector &Operands) { in parseBitfield() argument
4861 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc)); in parseBitfield()
4867 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) { in parsePostIdxReg() argument
4910 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, in parsePostIdxReg()
4917 ARMAsmParser::parseAM3Offset(OperandVector &Operands) { in parseAM3Offset() argument
4955 Operands.push_back( in parseAM3Offset()
4981 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, in parseAM3Offset()
4991 const OperandVector &Operands) { in cvtThumbMultiply() argument
4992 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); in cvtThumbMultiply()
4993 ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1); in cvtThumbMultiply()
4997 if (Operands.size() == 6 && in cvtThumbMultiply()
4998 ((ARMOperand &)*Operands[4]).getReg() == in cvtThumbMultiply()
4999 ((ARMOperand &)*Operands[3]).getReg()) in cvtThumbMultiply()
5001 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1); in cvtThumbMultiply()
5003 ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2); in cvtThumbMultiply()
5007 const OperandVector &Operands) { in cvtThumbBranches() argument
5030 unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode(); in cvtThumbBranches()
5047 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); in cvtThumbBranches()
5054 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); in cvtThumbBranches()
5060 ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1); in cvtThumbBranches()
5061 ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2); in cvtThumbBranches()
5066 bool ARMAsmParser::parseMemory(OperandVector &Operands) { in parseMemory() argument
5089 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0, in parseMemory()
5096 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); in parseMemory()
5146 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0, in parseMemory()
5153 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); in parseMemory()
5197 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0, in parseMemory()
5204 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); in parseMemory()
5241 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum, in parseMemory()
5248 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); in parseMemory()
5321 ARMAsmParser::parseFPImm(OperandVector &Operands) { in parseFPImm() argument
5348 ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]); in parseFPImm()
5352 ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]); in parseFPImm()
5374 Operands.push_back(ARMOperand::CreateImm( in parseFPImm()
5391 Operands.push_back(ARMOperand::CreateImm( in parseFPImm()
5403 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { in parseOperand() argument
5409 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); in parseOperand()
5428 if (!tryParseRegisterWithWriteBack(Operands)) in parseOperand()
5430 int Res = tryParseShiftRegister(Operands); in parseOperand()
5440 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S)); in parseOperand()
5460 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); in parseOperand()
5464 return parseMemory(Operands); in parseOperand()
5466 return parseRegisterList(Operands); in parseOperand()
5486 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); in parseOperand()
5492 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(), in parseOperand()
5517 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); in parseOperand()
5532 Operands.push_back(ARMOperand::CreateConstantPoolImm(SubExprVal, S, E)); in parseOperand()
5774 OperandVector &Operands) { in tryConvertingToTwoOperandForm() argument
5775 if (Operands.size() != 6) in tryConvertingToTwoOperandForm()
5778 const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]); in tryConvertingToTwoOperandForm()
5779 auto &Op4 = static_cast<ARMOperand &>(*Operands[4]); in tryConvertingToTwoOperandForm()
5790 auto &Op5 = static_cast<ARMOperand &>(*Operands[5]); in tryConvertingToTwoOperandForm()
5850 Operands.erase(Operands.begin() + 3); in tryConvertingToTwoOperandForm()
5855 OperandVector &Operands) { in shouldOmitCCOutOperand() argument
5867 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && in shouldOmitCCOutOperand()
5868 !static_cast<ARMOperand &>(*Operands[4]).isModImm() && in shouldOmitCCOutOperand()
5869 static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() && in shouldOmitCCOutOperand()
5870 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0) in shouldOmitCCOutOperand()
5875 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && in shouldOmitCCOutOperand()
5876 static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
5877 static_cast<ARMOperand &>(*Operands[4]).isReg() && in shouldOmitCCOutOperand()
5878 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0) in shouldOmitCCOutOperand()
5886 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
5887 static_cast<ARMOperand &>(*Operands[4]).isReg() && in shouldOmitCCOutOperand()
5888 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP && in shouldOmitCCOutOperand()
5889 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && in shouldOmitCCOutOperand()
5890 ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) || in shouldOmitCCOutOperand()
5891 static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4())) in shouldOmitCCOutOperand()
5899 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
5900 static_cast<ARMOperand &>(*Operands[4]).isReg() && in shouldOmitCCOutOperand()
5901 static_cast<ARMOperand &>(*Operands[5]).isImm()) { in shouldOmitCCOutOperand()
5907 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) && in shouldOmitCCOutOperand()
5908 isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) && in shouldOmitCCOutOperand()
5909 static_cast<ARMOperand &>(*Operands[5]).isImm0_7()) in shouldOmitCCOutOperand()
5913 if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC && in shouldOmitCCOutOperand()
5914 static_cast<ARMOperand &>(*Operands[5]).isT2SOImm()) in shouldOmitCCOutOperand()
5925 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && in shouldOmitCCOutOperand()
5926 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && in shouldOmitCCOutOperand()
5927 static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
5928 static_cast<ARMOperand &>(*Operands[4]).isReg() && in shouldOmitCCOutOperand()
5929 static_cast<ARMOperand &>(*Operands[5]).isReg() && in shouldOmitCCOutOperand()
5934 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || in shouldOmitCCOutOperand()
5935 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || in shouldOmitCCOutOperand()
5936 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) || in shouldOmitCCOutOperand()
5937 !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() != in shouldOmitCCOutOperand()
5938 static_cast<ARMOperand &>(*Operands[5]).getReg() && in shouldOmitCCOutOperand()
5939 static_cast<ARMOperand &>(*Operands[3]).getReg() != in shouldOmitCCOutOperand()
5940 static_cast<ARMOperand &>(*Operands[4]).getReg()))) in shouldOmitCCOutOperand()
5945 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 && in shouldOmitCCOutOperand()
5946 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && in shouldOmitCCOutOperand()
5947 static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
5948 static_cast<ARMOperand &>(*Operands[4]).isReg() && in shouldOmitCCOutOperand()
5952 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || in shouldOmitCCOutOperand()
5953 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || in shouldOmitCCOutOperand()
5963 (Operands.size() == 5 || Operands.size() == 6) && in shouldOmitCCOutOperand()
5964 static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
5965 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP && in shouldOmitCCOutOperand()
5966 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && in shouldOmitCCOutOperand()
5967 (static_cast<ARMOperand &>(*Operands[4]).isImm() || in shouldOmitCCOutOperand()
5968 (Operands.size() == 6 && in shouldOmitCCOutOperand()
5969 static_cast<ARMOperand &>(*Operands[5]).isImm()))) in shouldOmitCCOutOperand()
5976 OperandVector &Operands) { in shouldOmitPredicateOperand() argument
5980 (static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32" || in shouldOmitPredicateOperand()
5981 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f16")) { in shouldOmitPredicateOperand()
5982 if (static_cast<ARMOperand &>(*Operands[3]).isToken() && in shouldOmitPredicateOperand()
5983 (static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32" || in shouldOmitPredicateOperand()
5984 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f16")) in shouldOmitPredicateOperand()
5987 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() && in shouldOmitPredicateOperand()
5989 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) || in shouldOmitPredicateOperand()
5991 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()))) in shouldOmitPredicateOperand()
6025 OperandVector &Operands) { in fixupGNULDRDAlias() argument
6028 if (Operands.size() < 4) in fixupGNULDRDAlias()
6031 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]); in fixupGNULDRDAlias()
6032 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]); in fixupGNULDRDAlias()
6056 Operands.insert( in fixupGNULDRDAlias()
6057 Operands.begin() + 3, in fixupGNULDRDAlias()
6063 SMLoc NameLoc, OperandVector &Operands) { in ParseInstruction() argument
6101 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); in ParseInstruction()
6123 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); in ParseInstruction()
6155 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, in ParseInstruction()
6163 Operands.push_back(ARMOperand::CreateCondCode( in ParseInstruction()
6169 Operands.push_back(ARMOperand::CreateImm( in ParseInstruction()
6200 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); in ParseInstruction()
6207 if (parseOperand(Operands, Mnemonic)) { in ParseInstruction()
6213 if (parseOperand(Operands, Mnemonic)) { in ParseInstruction()
6222 tryConvertingToTwoOperandForm(Mnemonic, CarrySetting, Operands); in ParseInstruction()
6231 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) in ParseInstruction()
6232 Operands.erase(Operands.begin() + 1); in ParseInstruction()
6238 shouldOmitPredicateOperand(Mnemonic, Operands)) in ParseInstruction()
6239 Operands.erase(Operands.begin() + 1); in ParseInstruction()
6246 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && in ParseInstruction()
6247 static_cast<ARMOperand &>(*Operands[2]).isImm()) in ParseInstruction()
6248 Operands.erase(Operands.begin() + 1); in ParseInstruction()
6256 if (!isThumb() && Operands.size() > 4 && in ParseInstruction()
6261 ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]); in ParseInstruction()
6262 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]); in ParseInstruction()
6281 Operands[Idx] = in ParseInstruction()
6283 Operands.erase(Operands.begin() + Idx + 1); in ParseInstruction()
6288 fixupGNULDRDAlias(Mnemonic, Operands); in ParseInstruction()
6295 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 && in ParseInstruction()
6296 static_cast<ARMOperand &>(*Operands[3]).isReg() && in ParseInstruction()
6297 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC && in ParseInstruction()
6298 static_cast<ARMOperand &>(*Operands[4]).isReg() && in ParseInstruction()
6299 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR && in ParseInstruction()
6300 static_cast<ARMOperand &>(*Operands[5]).isImm()) { in ParseInstruction()
6301 Operands.front() = ARMOperand::CreateToken(Name, NameLoc); in ParseInstruction()
6302 Operands.erase(Operands.begin() + 1); in ParseInstruction()
6348 const OperandVector &Operands, in validatetLDMRegList() argument
6350 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]); in validatetLDMRegList()
6358 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), in validatetLDMRegList()
6361 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), in validatetLDMRegList()
6367 const OperandVector &Operands, in validatetSTMRegList() argument
6369 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]); in validatetSTMRegList()
6376 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), in validatetSTMRegList()
6379 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), in validatetSTMRegList()
6382 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), in validatetSTMRegList()
6388 const OperandVector &Operands, in validateLDRDSTRD() argument
6397 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
6402 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
6408 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
6411 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
6421 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
6430 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
6434 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
6448 const OperandVector &Operands) { in validateInstruction() argument
6450 SMLoc Loc = Operands[0]->getStartLoc(); in validateInstruction()
6464 for (unsigned I = 1; I < Operands.size(); ++I) in validateInstruction()
6465 if (static_cast<ARMOperand &>(*Operands[I]).isCondCode()) in validateInstruction()
6466 CondLoc = Operands[I]->getStartLoc(); in validateInstruction()
6508 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true, in validateInstruction()
6514 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true, in validateInstruction()
6519 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false, in validateInstruction()
6525 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false, in validateInstruction()
6533 return Error(Operands[2]->getStartLoc(), in validateInstruction()
6538 if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true, in validateInstruction()
6544 if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true, in validateInstruction()
6550 if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/false, in validateInstruction()
6575 return Error(Operands[3]->getStartLoc(), in validateInstruction()
6608 return Error(Operands[3]->getStartLoc(), in validateInstruction()
6620 return Error(Operands[5]->getStartLoc(), in validateInstruction()
6634 (static_cast<ARMOperand &>(*Operands[3]).isToken() && in validateInstruction()
6635 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!"); in validateInstruction()
6638 return Error(Operands[3 + HasWritebackToken]->getStartLoc(), in validateInstruction()
6642 return Error(Operands[2]->getStartLoc(), in validateInstruction()
6647 return Error(Operands[3]->getStartLoc(), in validateInstruction()
6651 if (validatetLDMRegList(Inst, Operands, 3)) in validateInstruction()
6664 return Error(Operands.back()->getStartLoc(), in validateInstruction()
6669 if (validatetLDMRegList(Inst, Operands, 3)) in validateInstruction()
6674 if (validatetSTMRegList(Inst, Operands, 3)) in validateInstruction()
6682 return Error(Operands.back()->getStartLoc(), in validateInstruction()
6686 if (validatetLDMRegList(Inst, Operands, 3)) in validateInstruction()
6689 if (validatetSTMRegList(Inst, Operands, 3)) in validateInstruction()
6699 return Error(Operands[4]->getStartLoc(), in validateInstruction()
6707 return Error(Operands[2]->getStartLoc(), in validateInstruction()
6718 if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() != in validateInstruction()
6719 ((ARMOperand &)*Operands[5]).getReg()) && in validateInstruction()
6720 (((ARMOperand &)*Operands[3]).getReg() != in validateInstruction()
6721 ((ARMOperand &)*Operands[4]).getReg())) { in validateInstruction()
6722 return Error(Operands[3]->getStartLoc(), in validateInstruction()
6734 return Error(Operands[2]->getStartLoc(), in validateInstruction()
6736 if (validatetLDMRegList(Inst, Operands, 2, !isMClass())) in validateInstruction()
6744 return Error(Operands[2]->getStartLoc(), in validateInstruction()
6746 if (validatetSTMRegList(Inst, Operands, 2)) in validateInstruction()
6755 return Error(Operands[4]->getStartLoc(), in validateInstruction()
6761 return Error(Operands[4]->getStartLoc(), in validateInstruction()
6765 if (validatetSTMRegList(Inst, Operands, 4)) in validateInstruction()
6774 return Error(Operands[4]->getStartLoc(), in validateInstruction()
6781 if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>()) in validateInstruction()
6782 return Error(Operands[2]->getStartLoc(), "branch target out of range"); in validateInstruction()
6785 int op = (Operands[2]->isImm()) ? 2 : 3; in validateInstruction()
6786 if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>()) in validateInstruction()
6787 return Error(Operands[op]->getStartLoc(), "branch target out of range"); in validateInstruction()
6792 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>()) in validateInstruction()
6793 return Error(Operands[2]->getStartLoc(), "branch target out of range"); in validateInstruction()
6796 int Op = (Operands[2]->isImm()) ? 2 : 3; in validateInstruction()
6797 if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>()) in validateInstruction()
6798 return Error(Operands[Op]->getStartLoc(), "branch target out of range"); in validateInstruction()
6803 if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<6, 1>()) in validateInstruction()
6804 return Error(Operands[2]->getStartLoc(), "branch target out of range"); in validateInstruction()
6818 int i = (Operands[3]->isImm()) ? 3 : 4; in validateInstruction()
6819 ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]); in validateInstruction()
6839 return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not " in validateInstruction()
6843 return Error(Operands[1]->getStartLoc(), "instruction 'csdb' is not " in validateInstruction()
6859 return Error(Operands[1]->getStartLoc(), in validateInstruction()
6863 return Error(Operands[1]->getStartLoc(), in validateInstruction()
6873 return Error(Operands[5]->getStartLoc(), in validateInstruction()
6882 return Error(Operands[3]->getStartLoc(), in validateInstruction()
6888 ARMOperand &Op = static_cast<ARMOperand&>(*Operands[3]); in validateInstruction()
6891 return Error(Operands[3]->getStartLoc(), in validateInstruction()
7157 const OperandVector &Operands, in processInstruction() argument
7162 for (auto &Op : Operands) { in processInstruction()
7281 static_cast<ARMOperand &>(*Operands[4]) : in processInstruction()
7282 static_cast<ARMOperand &>(*Operands[3])); in processInstruction()
8644 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" && in processInstruction()
8662 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" && in processInstruction()
8678 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" || in processInstruction()
8687 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" || in processInstruction()
8698 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { in processInstruction()
8708 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { in processInstruction()
8809 (static_cast<ARMOperand &>(*Operands[3]).isToken() && in processInstruction()
8810 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!"); in processInstruction()
9186 unsigned ARMAsmParser::MatchInstruction(OperandVector &Operands, MCInst &Inst, in MatchInstruction() argument
9193 return MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm); in MatchInstruction()
9199 if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) == in MatchInstruction()
9225 MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm); in MatchInstruction()
9252 if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) == in MatchInstruction()
9276 OperandVector &Operands, in MatchAndEmitInstruction() argument
9284 MatchResult = MatchInstruction(Operands, Inst, NearMisses, MatchingInlineAsm, in MatchAndEmitInstruction()
9295 if (validateInstruction(Inst, Operands)) { in MatchAndEmitInstruction()
9309 while (processInstruction(Inst, Operands, Out)) in MatchAndEmitInstruction()
9341 ReportNearMisses(NearMisses, IDLoc, Operands); in MatchAndEmitInstruction()
9346 ((ARMOperand &)*Operands[0]).getToken(), FBS); in MatchAndEmitInstruction()
9348 ((ARMOperand &)*Operands[0]).getLocRange()); in MatchAndEmitInstruction()
10024 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands; in parseDirectiveRegSave() local
10027 if (parseRegisterList(Operands) || in parseDirectiveRegSave()
10030 ARMOperand &Op = (ARMOperand &)*Operands[0]; in parseDirectiveRegSave()
10405 SMLoc IDLoc, OperandVector &Operands) { in FilterNearMisses() argument
10428 ((ARMOperand &)*Operands[I.getOperandIndex()]).getStartLoc(); in FilterNearMisses()
10545 SMLoc EndLoc = ((ARMOperand &)*Operands.back()).getEndLoc(); in FilterNearMisses()
10561 SMLoc IDLoc, OperandVector &Operands) { in ReportNearMisses() argument
10563 FilterNearMisses(NearMisses, Messages, IDLoc, Operands); in ReportNearMisses()