145   const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID);  in ARMRegisterBankInfo()  local
146   (void)RBGPR;  in ARMRegisterBankInfo()
147   assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up");  in ARMRegisterBankInfo()
150   assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) &&  in ARMRegisterBankInfo()
152   assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) &&  in ARMRegisterBankInfo()
154   assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) &&  in ARMRegisterBankInfo()
156   assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) &&  in ARMRegisterBankInfo()
158   assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) &&  in ARMRegisterBankInfo()
160   assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) &&  in ARMRegisterBankInfo()
162   assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPR_and_tcGPRRegClassID)) &&  in ARMRegisterBankInfo()
164   assert(RBGPR.getSize() == 32 && "GPRs should hold up to 32-bit");  in ARMRegisterBankInfo()