79           if (auto *Ld = dyn_cast<LoadInst>(V))  in SetMemoryLocations()
126     std::map<LoadInst*, LoadInst*> LoadPairs;
127     std::map<LoadInst*, SmallVector<LoadInst*, 4>> SequentialLoads;
131     bool AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1, MemInstList &VecMem);
133     Instruction *CreateSMLADCall(LoadInst *VecLd0, LoadInst *VecLd1,
283 bool ARMParallelDSP::AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1,  in AreSequentialLoads()
310   SmallVector<LoadInst*, 8> Loads;  in RecordSequentialLoads()
312     auto *Ld = dyn_cast<LoadInst>(&I);  in RecordSequentialLoads()
318   std::map<LoadInst*, LoadInst*> BaseLoads;  in RecordSequentialLoads()
325       if (AreSequentialAccesses<LoadInst>(Ld0, Ld1, *DL, *SE)) {  in RecordSequentialLoads()
328           LoadInst *Base = BaseLoads[Ld0];  in RecordSequentialLoads()
358       auto *Ld0 = dyn_cast<LoadInst>(PMul0->LHS[x]);  in CreateParallelMACPairs()
359       auto *Ld1 = dyn_cast<LoadInst>(PMul1->LHS[x]);  in CreateParallelMACPairs()
360       auto *Ld2 = dyn_cast<LoadInst>(PMul0->RHS[x]);  in CreateParallelMACPairs()
361       auto *Ld3 = dyn_cast<LoadInst>(PMul1->RHS[x]);  in CreateParallelMACPairs()
445     auto *VecLd0 = cast<LoadInst>(PMul0->VecLd[0]);  in InsertParallelMACs()
446     auto *VecLd1 = cast<LoadInst>(PMul1->VecLd[0]);  in InsertParallelMACs()
611       if (!isa<LoadInst>(LHS[i]) || !isa<LoadInst>(RHS[i]))  in CheckMACMemory()
691 static LoadInst *CreateLoadIns(IRBuilder<NoFolder> &IRB, LoadInst &BaseLoad,  in CreateLoadIns()
700 Instruction *ARMParallelDSP::CreateSMLADCall(LoadInst *VecLd0, LoadInst *VecLd1,  in CreateSMLADCall()
714   LoadInst *NewLd0 = CreateLoadIns(Builder, VecLd0[0], Ty);  in CreateSMLADCall()
715   LoadInst *NewLd1 = CreateLoadIns(Builder, VecLd1[0], Ty);  in CreateSMLADCall()