175         int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
180         int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
216   unsigned Opcode = MI.getOpcode();  in getMemoryOpOffset()  local
217   bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD;  in getMemoryOpOffset()
221   if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 ||  in getMemoryOpOffset()
222       Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 ||  in getMemoryOpOffset()
223       Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 ||  in getMemoryOpOffset()
224       Opcode == ARM::LDRi12   || Opcode == ARM::STRi12)  in getMemoryOpOffset()
228   if (Opcode == ARM::tLDRi || Opcode == ARM::tSTRi ||  in getMemoryOpOffset()
229       Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi)  in getMemoryOpOffset()
251 static int getLoadStoreMultipleOpcode(unsigned Opcode, ARM_AM::AMSubMode Mode) {  in getLoadStoreMultipleOpcode()  argument
252   switch (Opcode) {  in getLoadStoreMultipleOpcode()
336 static ARM_AM::AMSubMode getLoadStoreMultipleSubMode(unsigned Opcode) {  in getLoadStoreMultipleSubMode()  argument
337   switch (Opcode) {  in getLoadStoreMultipleSubMode()
624     int Offset, unsigned Base, bool BaseKill, unsigned Opcode,  in CreateLoadStoreMulti()  argument
643     if (Opcode == ARM::tLDRi)  in CreateLoadStoreMulti()
645     else if (Opcode == ARM::tSTRi)  in CreateLoadStoreMulti()
651   bool isNotVFP = isi32Load(Opcode) || isi32Store(Opcode);  in CreateLoadStoreMulti()
661   } else if (Offset != 0 || Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) {  in CreateLoadStoreMulti()
664     if (!getLoadStoreMultipleOpcode(Opcode, Mode)) return nullptr;  in CreateLoadStoreMulti()
678     if (isi32Load(Opcode)) {  in CreateLoadStoreMulti()
688       if (!isLoadSingle(Opcode))  in CreateLoadStoreMulti()
718       (!isi32Store(Opcode) || !ContainsReg(Regs, Base));  in CreateLoadStoreMulti()
768   bool isDef = isLoadSingle(Opcode);  in CreateLoadStoreMulti()
772   Opcode = getLoadStoreMultipleOpcode(Opcode, Mode);  in CreateLoadStoreMulti()
773   if (!Opcode)  in CreateLoadStoreMulti()
791     if (Opcode == ARM::tLDMIA) {  in CreateLoadStoreMulti()
794       Opcode = ARM::tLDMIA_UPD;  in CreateLoadStoreMulti()
797     MIB = BuildMI(MBB, InsertBefore, DL, TII->get(Opcode));  in CreateLoadStoreMulti()
809     MIB = BuildMI(MBB, InsertBefore, DL, TII->get(Opcode));  in CreateLoadStoreMulti()
823     int Offset, unsigned Base, bool BaseKill, unsigned Opcode,  in CreateLoadStoreDouble()  argument
826   bool IsLoad = isi32Load(Opcode);  in CreateLoadStoreDouble()
827   assert((IsLoad || isi32Store(Opcode)) && "Must have integer load or store");  in CreateLoadStoreDouble()
847   unsigned Opcode = First->getOpcode();  in MergeOpsUpdate()  local
848   bool IsLoad = isLoadSingle(Opcode);  in MergeOpsUpdate()
898                                    Opcode, Pred, PredReg, DL, Regs);  in MergeOpsUpdate()
901                                   Opcode, Pred, PredReg, DL, Regs);  in MergeOpsUpdate()
926   if (isLoadSingle(Opcode)) {  in MergeOpsUpdate()
947     assert(isi32Store(Opcode) || Opcode == ARM::VSTRS || Opcode == ARM::VSTRD);  in MergeOpsUpdate()
975   unsigned Opcode = MI.getOpcode();  in mayCombineMisaligned()  local
976   if (!isi32Load(Opcode) && !isi32Store(Opcode))  in mayCombineMisaligned()
990   unsigned Opcode = FirstMI->getOpcode();  in FormCandidates()  local
991   bool isNotVFP = isi32Load(Opcode) || isi32Store(Opcode);  in FormCandidates()
1011     if (STI->isCortexM3() && isi32Load(Opcode) &&  in FormCandidates()
1032     switch (Opcode) {  in FormCandidates()
1261   unsigned Opcode = MI->getOpcode();  in MergeBaseUpdateLSMultiple()  local
1276   ARM_AM::AMSubMode Mode = getLoadStoreMultipleSubMode(Opcode);  in MergeBaseUpdateLSMultiple()
1309   unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode);  in MergeBaseUpdateLSMultiple()
1385   unsigned Opcode = MI->getOpcode();  in MergeBaseUpdateLoadStore()  local
1387   bool isAM5 = (Opcode == ARM::VLDRD || Opcode == ARM::VLDRS ||  in MergeBaseUpdateLoadStore()
1388                 Opcode == ARM::VSTRD || Opcode == ARM::VSTRS);  in MergeBaseUpdateLoadStore()
1389   bool isAM2 = (Opcode == ARM::LDRi12 || Opcode == ARM::STRi12);  in MergeBaseUpdateLoadStore()
1390   if (isi32Load(Opcode) || isi32Store(Opcode))  in MergeBaseUpdateLoadStore()
1411     NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::add);  in MergeBaseUpdateLoadStore()
1413     NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::sub);  in MergeBaseUpdateLoadStore()
1417       NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::add);  in MergeBaseUpdateLoadStore()
1419       NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::sub);  in MergeBaseUpdateLoadStore()
1427   bool isLd = isLoadSingle(Opcode);  in MergeBaseUpdateLoadStore()
1493   unsigned Opcode = MI.getOpcode();  in MergeBaseUpdateLSDouble()  local
1494   assert((Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8) &&  in MergeBaseUpdateLSDouble()
1517     NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_PRE : ARM::t2STRD_PRE;  in MergeBaseUpdateLSDouble()
1521       NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_POST : ARM::t2STRD_POST;  in MergeBaseUpdateLSDouble()
1537   assert(TII->get(Opcode).getNumOperands() == 6 &&  in MergeBaseUpdateLSDouble()
1553   unsigned Opcode = MI.getOpcode();  in isMemoryOp()  local
1554   switch (Opcode) {  in isMemoryOp()
1629   unsigned Opcode = MI->getOpcode();  in FixInvalidRegPairOp()  local
1632   if (Opcode != ARM::LDRD && Opcode != ARM::STRD && Opcode != ARM::t2LDRDi8)  in FixInvalidRegPairOp()
1645     (Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8) && STI->isCortexM3();  in FixInvalidRegPairOp()
1647   bool NonConsecutiveRegs = (Opcode == ARM::LDRD || Opcode == ARM::STRD) &&  in FixInvalidRegPairOp()
1653   bool isT2 = Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8;  in FixInvalidRegPairOp()
1654   bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8;  in FixInvalidRegPairOp()
1757       unsigned Opcode = MBBI->getOpcode();  in LoadStoreMultipleOpti()  local
1767         CurrOpc  = Opcode;  in LoadStoreMultipleOpti()
1773       if (CurrOpc == Opcode && CurrBase == Base && CurrPred == Pred) {  in LoadStoreMultipleOpti()
1782         if (isLoadSingle(Opcode)) {  in LoadStoreMultipleOpti()
1861         unsigned Opcode = Merged->getOpcode();  in LoadStoreMultipleOpti()  local
1862         if (Opcode == ARM::t2STRDi8 || Opcode == ARM::t2LDRDi8)  in LoadStoreMultipleOpti()
1912     unsigned Opcode = PrevMI.getOpcode();  in MergeReturnIntoLDM()  local
1913     if (Opcode == ARM::LDMIA_UPD || Opcode == ARM::LDMDA_UPD ||  in MergeReturnIntoLDM()
1914         Opcode == ARM::LDMDB_UPD || Opcode == ARM::LDMIB_UPD ||  in MergeReturnIntoLDM()
1915         Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {  in MergeReturnIntoLDM()
1920       assert(((isThumb2 && Opcode == ARM::t2LDMIA_UPD) ||  in MergeReturnIntoLDM()
1921               Opcode == ARM::LDMIA_UPD) && "Unsupported multiple load-return!");  in MergeReturnIntoLDM()
2122   unsigned Opcode = Op0->getOpcode();  in CanFormLdStDWord()  local
2123   if (Opcode == ARM::LDRi12) {  in CanFormLdStDWord()
2125   } else if (Opcode == ARM::STRi12) {  in CanFormLdStDWord()
2127   } else if (Opcode == ARM::t2LDRi8 || Opcode == ARM::t2LDRi12) {  in CanFormLdStDWord()
2131   } else if (Opcode == ARM::t2STRi8 || Opcode == ARM::t2STRi12) {  in CanFormLdStDWord()