175         int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
180         int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
624     int Offset, unsigned Base, bool BaseKill, unsigned Opcode,  in CreateLoadStoreMulti()  argument
717     bool KillOldBase = BaseKill &&  in CreateLoadStoreMulti()
765     BaseKill = true; // New base is always killed straight away.  in CreateLoadStoreMulti()
784   if (isThumb1 && !SafeToClobberCPSR && Writeback && !BaseKill)  in CreateLoadStoreMulti()
801        .addReg(Base, getKillRegState(BaseKill));  in CreateLoadStoreMulti()
805     if (!BaseKill)  in CreateLoadStoreMulti()
810     MIB.addReg(Base, getKillRegState(BaseKill));  in CreateLoadStoreMulti()
823     int Offset, unsigned Base, bool BaseKill, unsigned Opcode,  in CreateLoadStoreDouble()  argument
891   bool BaseKill = LatestMI->killsRegister(Base);  in MergeOpsUpdate()  local
897     Merged = CreateLoadStoreDouble(MBB, InsertBefore, Offset, Base, BaseKill,  in MergeOpsUpdate()
900     Merged = CreateLoadStoreMulti(MBB, InsertBefore, Offset, Base, BaseKill,  in MergeOpsUpdate()
1258   bool BaseKill = BaseOP.isKill();  in MergeBaseUpdateLSMultiple()  local
1290       if (!MBB.getParent()->getFunction().optForMinSize() || !BaseKill)  in MergeBaseUpdateLSMultiple()
1312     .addReg(Base, getKillRegState(BaseKill))  in MergeBaseUpdateLSMultiple()
1384   bool BaseKill = getLoadStoreBaseOp(*MI).isKill();  in MergeBaseUpdateLoadStore()  local
1436       .addReg(Base, getKillRegState(isLd ? BaseKill : false))  in MergeBaseUpdateLoadStore()
1609                           bool BaseKill, bool BaseUndef, ARMCC::CondCodes Pred,  in InsertLDR_STR()  argument
1615       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));  in InsertLDR_STR()
1621       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));  in InsertLDR_STR()
1661   bool BaseKill = BaseOp.isKill();  in FixInvalidRegPairOp()  local
1677         .addReg(BaseReg, getKillRegState(BaseKill))  in FixInvalidRegPairOp()
1684         .addReg(BaseReg, getKillRegState(BaseKill))  in FixInvalidRegPairOp()
1709                     false, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII);  in FixInvalidRegPairOp()
1724                     OddUndef, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII);  in FixInvalidRegPairOp()