Lines Matching refs:Base
171 unsigned Base, unsigned WordOffset,
175 int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
180 int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
482 const DebugLoc &DL, unsigned Base, in UpdateBaseRegUses() argument
493 if (MBBI->readsRegister(Base)) { in UpdateBaseRegUses()
513 if (Offset >= 0 && !(IsStore && InstrSrcReg == Base)) in UpdateBaseRegUses()
549 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base) in UpdateBaseRegUses()
551 .addReg(Base) in UpdateBaseRegUses()
558 if (MBBI->killsRegister(Base) || MBBI->definesRegister(Base)) in UpdateBaseRegUses()
570 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base) in UpdateBaseRegUses()
572 .addReg(Base) in UpdateBaseRegUses()
624 int Offset, unsigned Base, bool BaseKill, unsigned Opcode, in CreateLoadStoreMulti() argument
641 if (isThumb1 && ContainsReg(Regs, Base)) { in CreateLoadStoreMulti()
642 assert(Base != ARM::SP && "Thumb1 does not allow SP in register list"); in CreateLoadStoreMulti()
699 (isThumb1 && Base == ARM::SP) ? ARM::tADDrSPi : in CreateLoadStoreMulti()
707 (isThumb1 && Offset < 8 && Base != ARM::SP) ? ARM::tSUBi3 : in CreateLoadStoreMulti()
718 (!isi32Store(Opcode) || !ContainsReg(Regs, Base)); in CreateLoadStoreMulti()
726 if (Base != NewBase && in CreateLoadStoreMulti()
729 if (isARMLowRegister(NewBase) && isARMLowRegister(Base) && in CreateLoadStoreMulti()
735 .addReg(Base, getKillRegState(KillOldBase)); in CreateLoadStoreMulti()
738 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti()
742 Base = NewBase; in CreateLoadStoreMulti()
748 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti()
754 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti()
759 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti()
764 Base = NewBase; in CreateLoadStoreMulti()
792 assert(!(ContainsReg(Regs, Base)) && "Thumb1 can't LDM ! with Base in Regs"); in CreateLoadStoreMulti()
800 MIB.addReg(Base, getDefRegState(true)) in CreateLoadStoreMulti()
801 .addReg(Base, getKillRegState(BaseKill)); in CreateLoadStoreMulti()
806 UpdateBaseRegUses(MBB, InsertBefore, DL, Base, NumRegs, Pred, PredReg); in CreateLoadStoreMulti()
810 MIB.addReg(Base, getKillRegState(BaseKill)); in CreateLoadStoreMulti()
823 int Offset, unsigned Base, bool BaseKill, unsigned Opcode, in CreateLoadStoreDouble() argument
840 MIB.addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg); in CreateLoadStoreDouble()
890 unsigned Base = getLoadStoreBaseOp(*First).getReg(); in MergeOpsUpdate() local
891 bool BaseKill = LatestMI->killsRegister(Base); in MergeOpsUpdate()
897 Merged = CreateLoadStoreDouble(MBB, InsertBefore, Offset, Base, BaseKill, in MergeOpsUpdate()
900 Merged = CreateLoadStoreMulti(MBB, InsertBefore, Offset, Base, BaseKill, in MergeOpsUpdate()
1257 unsigned Base = BaseOP.getReg(); in MergeBaseUpdateLSMultiple() local
1267 if (MI->getOperand(i).getReg() == Base) in MergeBaseUpdateLSMultiple()
1275 = findIncDecBefore(MBBI, Base, Pred, PredReg, Offset); in MergeBaseUpdateLSMultiple()
1282 MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset); in MergeBaseUpdateLSMultiple()
1311 .addReg(Base, getDefRegState(true)) // WB base register in MergeBaseUpdateLSMultiple()
1312 .addReg(Base, getKillRegState(BaseKill)) in MergeBaseUpdateLSMultiple()
1383 unsigned Base = getLoadStoreBaseOp(*MI).getReg(); in MergeBaseUpdateLoadStore() local
1398 if (MI->getOperand(0).getReg() == Base) in MergeBaseUpdateLoadStore()
1408 = findIncDecBefore(MBBI, Base, Pred, PredReg, Offset); in MergeBaseUpdateLoadStore()
1415 MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset); in MergeBaseUpdateLoadStore()
1435 .addReg(Base, getDefRegState(true)) // WB base register in MergeBaseUpdateLoadStore()
1436 .addReg(Base, getKillRegState(isLd ? BaseKill : false)) in MergeBaseUpdateLoadStore()
1445 .addReg(Base, RegState::Define) in MergeBaseUpdateLoadStore()
1446 .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg); in MergeBaseUpdateLoadStore()
1450 .addReg(Base, RegState::Define) in MergeBaseUpdateLoadStore()
1451 .addReg(Base) in MergeBaseUpdateLoadStore()
1459 .addReg(Base, RegState::Define) in MergeBaseUpdateLoadStore()
1460 .addReg(Base) in MergeBaseUpdateLoadStore()
1472 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), Base) in MergeBaseUpdateLoadStore()
1474 .addReg(Base) in MergeBaseUpdateLoadStore()
1480 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), Base) in MergeBaseUpdateLoadStore()
1482 .addReg(Base) in MergeBaseUpdateLoadStore()
1502 unsigned Base = BaseOp.getReg(); in MergeBaseUpdateLSDouble() local
1505 if (Reg0Op.getReg() == Base || Reg1Op.getReg() == Base) in MergeBaseUpdateLSDouble()
1513 MachineBasicBlock::iterator MergeInstr = findIncDecBefore(MBBI, Base, Pred, in MergeBaseUpdateLSDouble()
1519 MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset); in MergeBaseUpdateLSDouble()
1760 unsigned Base = getLoadStoreBaseOp(*MBBI).getReg(); in LoadStoreMultipleOpti() local
1766 CurrBase = Base; in LoadStoreMultipleOpti()
1773 if (CurrOpc == Opcode && CurrBase == Base && CurrPred == Pred) { in LoadStoreMultipleOpti()
1783 Overlap = (Base == Reg); in LoadStoreMultipleOpti()
2039 unsigned Base, bool isLd,
2070 static bool IsSafeAndProfitableToMove(bool isLd, unsigned Base, in IsSafeAndProfitableToMove() argument
2093 if (MO.isDef() && TRI->regsOverlap(Reg, Base)) in IsSafeAndProfitableToMove()
2095 if (Reg != Base && !MemRegs.count(Reg)) in IsSafeAndProfitableToMove()
2184 unsigned Base, bool isLd, in RescheduleOps() argument
2260 DoMove = IsSafeAndProfitableToMove(isLd, Base, FirstOp, LastOp, in RescheduleOps()
2382 unsigned Base = MI.getOperand(1).getReg(); in RescheduleLoadStoreInstrs() local
2388 Base2LdsMap.find(Base); in RescheduleLoadStoreInstrs()
2399 Base2LdsMap[Base].push_back(&MI); in RescheduleLoadStoreInstrs()
2400 LdBases.push_back(Base); in RescheduleLoadStoreInstrs()
2404 Base2StsMap.find(Base); in RescheduleLoadStoreInstrs()
2415 Base2StsMap[Base].push_back(&MI); in RescheduleLoadStoreInstrs()
2416 StBases.push_back(Base); in RescheduleLoadStoreInstrs()
2430 unsigned Base = LdBases[i]; in RescheduleLoadStoreInstrs() local
2431 SmallVectorImpl<MachineInstr *> &Lds = Base2LdsMap[Base]; in RescheduleLoadStoreInstrs()
2433 RetVal |= RescheduleOps(MBB, Lds, Base, true, MI2LocMap); in RescheduleLoadStoreInstrs()
2438 unsigned Base = StBases[i]; in RescheduleLoadStoreInstrs() local
2439 SmallVectorImpl<MachineInstr *> &Sts = Base2StsMap[Base]; in RescheduleLoadStoreInstrs()
2441 RetVal |= RescheduleOps(MBB, Sts, Base, false, MI2LocMap); in RescheduleLoadStoreInstrs()