Lines Matching refs:setTargetDAGCombine
705 setTargetDAGCombine(ISD::INTRINSIC_VOID); in ARMTargetLowering()
706 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN); in ARMTargetLowering()
707 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); in ARMTargetLowering()
708 setTargetDAGCombine(ISD::SHL); in ARMTargetLowering()
709 setTargetDAGCombine(ISD::SRL); in ARMTargetLowering()
710 setTargetDAGCombine(ISD::SRA); in ARMTargetLowering()
711 setTargetDAGCombine(ISD::SIGN_EXTEND); in ARMTargetLowering()
712 setTargetDAGCombine(ISD::ZERO_EXTEND); in ARMTargetLowering()
713 setTargetDAGCombine(ISD::ANY_EXTEND); in ARMTargetLowering()
714 setTargetDAGCombine(ISD::BUILD_VECTOR); in ARMTargetLowering()
715 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); in ARMTargetLowering()
716 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); in ARMTargetLowering()
717 setTargetDAGCombine(ISD::STORE); in ARMTargetLowering()
718 setTargetDAGCombine(ISD::FP_TO_SINT); in ARMTargetLowering()
719 setTargetDAGCombine(ISD::FP_TO_UINT); in ARMTargetLowering()
720 setTargetDAGCombine(ISD::FDIV); in ARMTargetLowering()
721 setTargetDAGCombine(ISD::LOAD); in ARMTargetLowering()
1171 setTargetDAGCombine(ISD::ADD); in ARMTargetLowering()
1172 setTargetDAGCombine(ISD::SUB); in ARMTargetLowering()
1173 setTargetDAGCombine(ISD::MUL); in ARMTargetLowering()
1174 setTargetDAGCombine(ISD::AND); in ARMTargetLowering()
1175 setTargetDAGCombine(ISD::OR); in ARMTargetLowering()
1176 setTargetDAGCombine(ISD::XOR); in ARMTargetLowering()
1179 setTargetDAGCombine(ISD::SRL); in ARMTargetLowering()