Lines Matching refs:isSEXTLoad
7210 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N)) in isSignExtended()
7301 assert((ISD::isSEXTLoad(LD) || ISD::isZEXTLoad(LD)) && in SkipExtensionForVMULL()
7306 unsigned Opcode = ISD::isSEXTLoad(LD) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in SkipExtensionForVMULL()
13363 bool isSEXTLoad, SDValue &Base, in getARMIndexedAddressParts() argument
13369 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { in getARMIndexedAddressParts()
13422 bool isSEXTLoad, SDValue &Base, in getT2IndexedAddressParts() argument
13459 bool isSEXTLoad = false; in getPreIndexedAddressParts() local
13463 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; in getPreIndexedAddressParts()
13473 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, in getPreIndexedAddressParts()
13476 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, in getPreIndexedAddressParts()
13495 bool isSEXTLoad = false, isNonExt; in getPostIndexedAddressParts() local
13499 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; in getPostIndexedAddressParts()
13527 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, in getPostIndexedAddressParts()
13530 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, in getPostIndexedAddressParts()