Lines Matching refs:MVT
149 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT, in addTypeForNEON()
150 MVT PromotedBitwiseVT) { in addTypeForNEON()
159 MVT ElemTy = VT.getVectorElementType(); in addTypeForNEON()
160 if (ElemTy != MVT::f64) in addTypeForNEON()
164 if (ElemTy == MVT::i32) { in addTypeForNEON()
208 VT != MVT::v2i64 && VT != MVT::v1i64) in addTypeForNEON()
213 void ARMTargetLowering::addDRTypeForNEON(MVT VT) { in addDRTypeForNEON()
215 addTypeForNEON(VT, MVT::f64, MVT::v2i32); in addDRTypeForNEON()
218 void ARMTargetLowering::addQRTypeForNEON(MVT VT) { in addQRTypeForNEON()
220 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); in addQRTypeForNEON()
508 addRegisterClass(MVT::i32, &ARM::tGPRRegClass); in ARMTargetLowering()
510 addRegisterClass(MVT::i32, &ARM::GPRRegClass); in ARMTargetLowering()
514 addRegisterClass(MVT::f32, &ARM::SPRRegClass); in ARMTargetLowering()
515 addRegisterClass(MVT::f64, &ARM::DPRRegClass); in ARMTargetLowering()
519 addRegisterClass(MVT::f16, &ARM::HPRRegClass); in ARMTargetLowering()
520 setOperationAction(ISD::BITCAST, MVT::i16, Custom); in ARMTargetLowering()
521 setOperationAction(ISD::BITCAST, MVT::i32, Custom); in ARMTargetLowering()
522 setOperationAction(ISD::BITCAST, MVT::f16, Custom); in ARMTargetLowering()
524 setOperationAction(ISD::FMINNUM, MVT::f16, Legal); in ARMTargetLowering()
525 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal); in ARMTargetLowering()
528 for (MVT VT : MVT::vector_valuetypes()) { in ARMTargetLowering()
529 for (MVT InnerVT : MVT::vector_valuetypes()) { in ARMTargetLowering()
544 setOperationAction(ISD::ConstantFP, MVT::f32, Custom); in ARMTargetLowering()
545 setOperationAction(ISD::ConstantFP, MVT::f64, Custom); in ARMTargetLowering()
547 setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom); in ARMTargetLowering()
548 setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom); in ARMTargetLowering()
551 addDRTypeForNEON(MVT::v2f32); in ARMTargetLowering()
552 addDRTypeForNEON(MVT::v8i8); in ARMTargetLowering()
553 addDRTypeForNEON(MVT::v4i16); in ARMTargetLowering()
554 addDRTypeForNEON(MVT::v2i32); in ARMTargetLowering()
555 addDRTypeForNEON(MVT::v1i64); in ARMTargetLowering()
557 addQRTypeForNEON(MVT::v4f32); in ARMTargetLowering()
558 addQRTypeForNEON(MVT::v2f64); in ARMTargetLowering()
559 addQRTypeForNEON(MVT::v16i8); in ARMTargetLowering()
560 addQRTypeForNEON(MVT::v8i16); in ARMTargetLowering()
561 addQRTypeForNEON(MVT::v4i32); in ARMTargetLowering()
562 addQRTypeForNEON(MVT::v2i64); in ARMTargetLowering()
565 addQRTypeForNEON(MVT::v8f16); in ARMTargetLowering()
566 addDRTypeForNEON(MVT::v4f16); in ARMTargetLowering()
573 setOperationAction(ISD::FADD, MVT::v2f64, Expand); in ARMTargetLowering()
574 setOperationAction(ISD::FSUB, MVT::v2f64, Expand); in ARMTargetLowering()
575 setOperationAction(ISD::FMUL, MVT::v2f64, Expand); in ARMTargetLowering()
578 setOperationAction(ISD::FDIV, MVT::v2f64, Expand); in ARMTargetLowering()
579 setOperationAction(ISD::FREM, MVT::v2f64, Expand); in ARMTargetLowering()
583 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand); in ARMTargetLowering()
586 setOperationAction(ISD::SETCC, MVT::v2f64, Expand); in ARMTargetLowering()
588 setOperationAction(ISD::FNEG, MVT::v2f64, Expand); in ARMTargetLowering()
589 setOperationAction(ISD::FABS, MVT::v2f64, Expand); in ARMTargetLowering()
590 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand); in ARMTargetLowering()
591 setOperationAction(ISD::FSIN, MVT::v2f64, Expand); in ARMTargetLowering()
592 setOperationAction(ISD::FCOS, MVT::v2f64, Expand); in ARMTargetLowering()
593 setOperationAction(ISD::FPOW, MVT::v2f64, Expand); in ARMTargetLowering()
594 setOperationAction(ISD::FLOG, MVT::v2f64, Expand); in ARMTargetLowering()
595 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand); in ARMTargetLowering()
596 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand); in ARMTargetLowering()
597 setOperationAction(ISD::FEXP, MVT::v2f64, Expand); in ARMTargetLowering()
598 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand); in ARMTargetLowering()
600 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand); in ARMTargetLowering()
601 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand); in ARMTargetLowering()
602 setOperationAction(ISD::FRINT, MVT::v2f64, Expand); in ARMTargetLowering()
603 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand); in ARMTargetLowering()
604 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand); in ARMTargetLowering()
605 setOperationAction(ISD::FMA, MVT::v2f64, Expand); in ARMTargetLowering()
607 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand); in ARMTargetLowering()
608 setOperationAction(ISD::FSIN, MVT::v4f32, Expand); in ARMTargetLowering()
609 setOperationAction(ISD::FCOS, MVT::v4f32, Expand); in ARMTargetLowering()
610 setOperationAction(ISD::FPOW, MVT::v4f32, Expand); in ARMTargetLowering()
611 setOperationAction(ISD::FLOG, MVT::v4f32, Expand); in ARMTargetLowering()
612 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand); in ARMTargetLowering()
613 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand); in ARMTargetLowering()
614 setOperationAction(ISD::FEXP, MVT::v4f32, Expand); in ARMTargetLowering()
615 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand); in ARMTargetLowering()
616 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand); in ARMTargetLowering()
617 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand); in ARMTargetLowering()
618 setOperationAction(ISD::FRINT, MVT::v4f32, Expand); in ARMTargetLowering()
619 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand); in ARMTargetLowering()
620 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand); in ARMTargetLowering()
623 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand); in ARMTargetLowering()
624 setOperationAction(ISD::FSIN, MVT::v2f32, Expand); in ARMTargetLowering()
625 setOperationAction(ISD::FCOS, MVT::v2f32, Expand); in ARMTargetLowering()
626 setOperationAction(ISD::FPOW, MVT::v2f32, Expand); in ARMTargetLowering()
627 setOperationAction(ISD::FLOG, MVT::v2f32, Expand); in ARMTargetLowering()
628 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand); in ARMTargetLowering()
629 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand); in ARMTargetLowering()
630 setOperationAction(ISD::FEXP, MVT::v2f32, Expand); in ARMTargetLowering()
631 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand); in ARMTargetLowering()
632 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand); in ARMTargetLowering()
633 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand); in ARMTargetLowering()
634 setOperationAction(ISD::FRINT, MVT::v2f32, Expand); in ARMTargetLowering()
635 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand); in ARMTargetLowering()
636 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand); in ARMTargetLowering()
639 setOperationAction(ISD::MUL, MVT::v1i64, Expand); in ARMTargetLowering()
641 setOperationAction(ISD::MUL, MVT::v8i16, Custom); in ARMTargetLowering()
642 setOperationAction(ISD::MUL, MVT::v4i32, Custom); in ARMTargetLowering()
643 setOperationAction(ISD::MUL, MVT::v2i64, Custom); in ARMTargetLowering()
645 setOperationAction(ISD::SDIV, MVT::v4i16, Custom); in ARMTargetLowering()
646 setOperationAction(ISD::SDIV, MVT::v8i8, Custom); in ARMTargetLowering()
647 setOperationAction(ISD::UDIV, MVT::v4i16, Custom); in ARMTargetLowering()
648 setOperationAction(ISD::UDIV, MVT::v8i8, Custom); in ARMTargetLowering()
653 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom); in ARMTargetLowering()
654 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Custom); in ARMTargetLowering()
655 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); in ARMTargetLowering()
656 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom); in ARMTargetLowering()
657 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom); in ARMTargetLowering()
658 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Custom); in ARMTargetLowering()
659 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom); in ARMTargetLowering()
660 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom); in ARMTargetLowering()
662 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand); in ARMTargetLowering()
663 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand); in ARMTargetLowering()
668 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom); in ARMTargetLowering()
669 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom); in ARMTargetLowering()
670 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom); in ARMTargetLowering()
671 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom); in ARMTargetLowering()
672 setOperationAction(ISD::CTPOP, MVT::v1i64, Custom); in ARMTargetLowering()
673 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom); in ARMTargetLowering()
675 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand); in ARMTargetLowering()
676 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand); in ARMTargetLowering()
679 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom); in ARMTargetLowering()
680 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom); in ARMTargetLowering()
681 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom); in ARMTargetLowering()
682 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom); in ARMTargetLowering()
684 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom); in ARMTargetLowering()
685 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom); in ARMTargetLowering()
686 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom); in ARMTargetLowering()
687 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom); in ARMTargetLowering()
689 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom); in ARMTargetLowering()
690 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom); in ARMTargetLowering()
691 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom); in ARMTargetLowering()
692 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom); in ARMTargetLowering()
694 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom); in ARMTargetLowering()
695 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom); in ARMTargetLowering()
696 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom); in ARMTargetLowering()
697 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom); in ARMTargetLowering()
701 setOperationAction(ISD::FMA, MVT::v2f32, Expand); in ARMTargetLowering()
702 setOperationAction(ISD::FMA, MVT::v4f32, Expand); in ARMTargetLowering()
724 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16, in ARMTargetLowering()
725 MVT::v2i32}) { in ARMTargetLowering()
726 for (MVT VT : MVT::integer_vector_valuetypes()) { in ARMTargetLowering()
739 setOperationAction(ISD::FADD, MVT::f64, Expand); in ARMTargetLowering()
740 setOperationAction(ISD::FSUB, MVT::f64, Expand); in ARMTargetLowering()
741 setOperationAction(ISD::FMUL, MVT::f64, Expand); in ARMTargetLowering()
742 setOperationAction(ISD::FMA, MVT::f64, Expand); in ARMTargetLowering()
743 setOperationAction(ISD::FDIV, MVT::f64, Expand); in ARMTargetLowering()
744 setOperationAction(ISD::FREM, MVT::f64, Expand); in ARMTargetLowering()
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in ARMTargetLowering()
746 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand); in ARMTargetLowering()
747 setOperationAction(ISD::FNEG, MVT::f64, Expand); in ARMTargetLowering()
748 setOperationAction(ISD::FABS, MVT::f64, Expand); in ARMTargetLowering()
749 setOperationAction(ISD::FSQRT, MVT::f64, Expand); in ARMTargetLowering()
750 setOperationAction(ISD::FSIN, MVT::f64, Expand); in ARMTargetLowering()
751 setOperationAction(ISD::FCOS, MVT::f64, Expand); in ARMTargetLowering()
752 setOperationAction(ISD::FPOW, MVT::f64, Expand); in ARMTargetLowering()
753 setOperationAction(ISD::FLOG, MVT::f64, Expand); in ARMTargetLowering()
754 setOperationAction(ISD::FLOG2, MVT::f64, Expand); in ARMTargetLowering()
755 setOperationAction(ISD::FLOG10, MVT::f64, Expand); in ARMTargetLowering()
756 setOperationAction(ISD::FEXP, MVT::f64, Expand); in ARMTargetLowering()
757 setOperationAction(ISD::FEXP2, MVT::f64, Expand); in ARMTargetLowering()
758 setOperationAction(ISD::FCEIL, MVT::f64, Expand); in ARMTargetLowering()
759 setOperationAction(ISD::FTRUNC, MVT::f64, Expand); in ARMTargetLowering()
760 setOperationAction(ISD::FRINT, MVT::f64, Expand); in ARMTargetLowering()
761 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand); in ARMTargetLowering()
762 setOperationAction(ISD::FFLOOR, MVT::f64, Expand); in ARMTargetLowering()
763 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in ARMTargetLowering()
764 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in ARMTargetLowering()
765 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in ARMTargetLowering()
766 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in ARMTargetLowering()
767 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom); in ARMTargetLowering()
768 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom); in ARMTargetLowering()
769 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in ARMTargetLowering()
770 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom); in ARMTargetLowering()
776 for (MVT VT : MVT::fp_valuetypes()) { in ARMTargetLowering()
777 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in ARMTargetLowering()
778 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); in ARMTargetLowering()
782 setTruncStoreAction(MVT::f64, MVT::f32, Expand); in ARMTargetLowering()
783 setTruncStoreAction(MVT::f32, MVT::f16, Expand); in ARMTargetLowering()
784 setTruncStoreAction(MVT::f64, MVT::f16, Expand); in ARMTargetLowering()
787 for (MVT VT : MVT::integer_valuetypes()) in ARMTargetLowering()
788 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in ARMTargetLowering()
794 setIndexedLoadAction(im, MVT::i1, Legal); in ARMTargetLowering()
795 setIndexedLoadAction(im, MVT::i8, Legal); in ARMTargetLowering()
796 setIndexedLoadAction(im, MVT::i16, Legal); in ARMTargetLowering()
797 setIndexedLoadAction(im, MVT::i32, Legal); in ARMTargetLowering()
798 setIndexedStoreAction(im, MVT::i1, Legal); in ARMTargetLowering()
799 setIndexedStoreAction(im, MVT::i8, Legal); in ARMTargetLowering()
800 setIndexedStoreAction(im, MVT::i16, Legal); in ARMTargetLowering()
801 setIndexedStoreAction(im, MVT::i32, Legal); in ARMTargetLowering()
805 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal); in ARMTargetLowering()
806 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal); in ARMTargetLowering()
809 setOperationAction(ISD::SADDO, MVT::i32, Custom); in ARMTargetLowering()
810 setOperationAction(ISD::UADDO, MVT::i32, Custom); in ARMTargetLowering()
811 setOperationAction(ISD::SSUBO, MVT::i32, Custom); in ARMTargetLowering()
812 setOperationAction(ISD::USUBO, MVT::i32, Custom); in ARMTargetLowering()
814 setOperationAction(ISD::ADDCARRY, MVT::i32, Custom); in ARMTargetLowering()
815 setOperationAction(ISD::SUBCARRY, MVT::i32, Custom); in ARMTargetLowering()
818 setOperationAction(ISD::MUL, MVT::i64, Expand); in ARMTargetLowering()
819 setOperationAction(ISD::MULHU, MVT::i32, Expand); in ARMTargetLowering()
821 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); in ARMTargetLowering()
822 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); in ARMTargetLowering()
826 setOperationAction(ISD::MULHS, MVT::i32, Expand); in ARMTargetLowering()
828 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); in ARMTargetLowering()
829 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); in ARMTargetLowering()
830 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); in ARMTargetLowering()
831 setOperationAction(ISD::SRL, MVT::i64, Custom); in ARMTargetLowering()
832 setOperationAction(ISD::SRA, MVT::i64, Custom); in ARMTargetLowering()
833 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom); in ARMTargetLowering()
837 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); in ARMTargetLowering()
838 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); in ARMTargetLowering()
839 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); in ARMTargetLowering()
843 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); in ARMTargetLowering()
846 setOperationAction(ISD::ROTL, MVT::i32, Expand); in ARMTargetLowering()
847 for (MVT VT : MVT::vector_valuetypes()) { in ARMTargetLowering()
851 setOperationAction(ISD::CTTZ, MVT::i32, Custom); in ARMTargetLowering()
852 setOperationAction(ISD::CTPOP, MVT::i32, Expand); in ARMTargetLowering()
854 setOperationAction(ISD::CTLZ, MVT::i32, Expand); in ARMTargetLowering()
855 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, LibCall); in ARMTargetLowering()
863 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom); in ARMTargetLowering()
867 setOperationAction(ISD::BSWAP, MVT::i32, Expand); in ARMTargetLowering()
873 setOperationAction(ISD::SDIV, MVT::i32, LibCall); in ARMTargetLowering()
874 setOperationAction(ISD::UDIV, MVT::i32, LibCall); in ARMTargetLowering()
878 setOperationAction(ISD::SDIV, MVT::i32, Custom); in ARMTargetLowering()
879 setOperationAction(ISD::UDIV, MVT::i32, Custom); in ARMTargetLowering()
881 setOperationAction(ISD::SDIV, MVT::i64, Custom); in ARMTargetLowering()
882 setOperationAction(ISD::UDIV, MVT::i64, Custom); in ARMTargetLowering()
885 setOperationAction(ISD::SREM, MVT::i32, Expand); in ARMTargetLowering()
886 setOperationAction(ISD::UREM, MVT::i32, Expand); in ARMTargetLowering()
892 setOperationAction(ISD::SREM, MVT::i64, Custom); in ARMTargetLowering()
893 setOperationAction(ISD::UREM, MVT::i64, Custom); in ARMTargetLowering()
940 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); in ARMTargetLowering()
941 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); in ARMTargetLowering()
942 setOperationAction(ISD::SDIVREM, MVT::i64, Custom); in ARMTargetLowering()
943 setOperationAction(ISD::UDIVREM, MVT::i64, Custom); in ARMTargetLowering()
945 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in ARMTargetLowering()
946 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in ARMTargetLowering()
950 for (auto &VT : {MVT::f32, MVT::f64}) in ARMTargetLowering()
953 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); in ARMTargetLowering()
954 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); in ARMTargetLowering()
955 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); in ARMTargetLowering()
956 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); in ARMTargetLowering()
958 setOperationAction(ISD::TRAP, MVT::Other, Legal); in ARMTargetLowering()
959 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal); in ARMTargetLowering()
962 setOperationAction(ISD::VASTART, MVT::Other, Custom); in ARMTargetLowering()
963 setOperationAction(ISD::VAARG, MVT::Other, Expand); in ARMTargetLowering()
964 setOperationAction(ISD::VACOPY, MVT::Other, Expand); in ARMTargetLowering()
965 setOperationAction(ISD::VAEND, MVT::Other, Expand); in ARMTargetLowering()
966 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); in ARMTargetLowering()
967 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); in ARMTargetLowering()
970 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); in ARMTargetLowering()
972 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); in ARMTargetLowering()
981 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); in ARMTargetLowering()
983 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom); in ARMTargetLowering()
999 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, in ARMTargetLowering()
1003 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand); in ARMTargetLowering()
1004 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand); in ARMTargetLowering()
1005 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand); in ARMTargetLowering()
1006 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand); in ARMTargetLowering()
1007 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand); in ARMTargetLowering()
1008 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand); in ARMTargetLowering()
1009 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand); in ARMTargetLowering()
1010 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand); in ARMTargetLowering()
1011 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand); in ARMTargetLowering()
1012 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand); in ARMTargetLowering()
1013 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand); in ARMTargetLowering()
1014 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand); in ARMTargetLowering()
1018 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom); in ARMTargetLowering()
1019 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom); in ARMTargetLowering()
1023 setOperationAction(ISD::PREFETCH, MVT::Other, Custom); in ARMTargetLowering()
1027 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in ARMTargetLowering()
1028 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in ARMTargetLowering()
1030 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in ARMTargetLowering()
1036 setOperationAction(ISD::BITCAST, MVT::i64, Custom); in ARMTargetLowering()
1037 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); in ARMTargetLowering()
1041 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in ARMTargetLowering()
1042 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom); in ARMTargetLowering()
1043 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom); in ARMTargetLowering()
1044 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom); in ARMTargetLowering()
1048 setOperationAction(ISD::SETCC, MVT::i32, Expand); in ARMTargetLowering()
1049 setOperationAction(ISD::SETCC, MVT::f32, Expand); in ARMTargetLowering()
1050 setOperationAction(ISD::SETCC, MVT::f64, Expand); in ARMTargetLowering()
1051 setOperationAction(ISD::SELECT, MVT::i32, Custom); in ARMTargetLowering()
1052 setOperationAction(ISD::SELECT, MVT::f32, Custom); in ARMTargetLowering()
1053 setOperationAction(ISD::SELECT, MVT::f64, Custom); in ARMTargetLowering()
1054 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in ARMTargetLowering()
1055 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in ARMTargetLowering()
1056 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in ARMTargetLowering()
1058 setOperationAction(ISD::SETCC, MVT::f16, Expand); in ARMTargetLowering()
1059 setOperationAction(ISD::SELECT, MVT::f16, Custom); in ARMTargetLowering()
1060 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom); in ARMTargetLowering()
1063 setOperationAction(ISD::SETCCCARRY, MVT::i32, Custom); in ARMTargetLowering()
1065 setOperationAction(ISD::BRCOND, MVT::Other, Custom); in ARMTargetLowering()
1066 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in ARMTargetLowering()
1068 setOperationAction(ISD::BR_CC, MVT::f16, Custom); in ARMTargetLowering()
1069 setOperationAction(ISD::BR_CC, MVT::f32, Custom); in ARMTargetLowering()
1070 setOperationAction(ISD::BR_CC, MVT::f64, Custom); in ARMTargetLowering()
1071 setOperationAction(ISD::BR_JT, MVT::Other, Custom); in ARMTargetLowering()
1074 setOperationAction(ISD::FSIN, MVT::f64, Expand); in ARMTargetLowering()
1075 setOperationAction(ISD::FSIN, MVT::f32, Expand); in ARMTargetLowering()
1076 setOperationAction(ISD::FCOS, MVT::f32, Expand); in ARMTargetLowering()
1077 setOperationAction(ISD::FCOS, MVT::f64, Expand); in ARMTargetLowering()
1078 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in ARMTargetLowering()
1079 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in ARMTargetLowering()
1080 setOperationAction(ISD::FREM, MVT::f64, Expand); in ARMTargetLowering()
1081 setOperationAction(ISD::FREM, MVT::f32, Expand); in ARMTargetLowering()
1084 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); in ARMTargetLowering()
1085 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); in ARMTargetLowering()
1087 setOperationAction(ISD::FPOW, MVT::f64, Expand); in ARMTargetLowering()
1088 setOperationAction(ISD::FPOW, MVT::f32, Expand); in ARMTargetLowering()
1091 setOperationAction(ISD::FMA, MVT::f64, Expand); in ARMTargetLowering()
1092 setOperationAction(ISD::FMA, MVT::f32, Expand); in ARMTargetLowering()
1099 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); in ARMTargetLowering()
1100 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in ARMTargetLowering()
1105 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); in ARMTargetLowering()
1106 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in ARMTargetLowering()
1113 setOperationAction(ISD::FSINCOS, MVT::f64, Custom); in ARMTargetLowering()
1114 setOperationAction(ISD::FSINCOS, MVT::f32, Custom); in ARMTargetLowering()
1119 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); in ARMTargetLowering()
1120 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in ARMTargetLowering()
1121 setOperationAction(ISD::FROUND, MVT::f32, Legal); in ARMTargetLowering()
1122 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); in ARMTargetLowering()
1123 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); in ARMTargetLowering()
1124 setOperationAction(ISD::FRINT, MVT::f32, Legal); in ARMTargetLowering()
1125 setOperationAction(ISD::FMINNUM, MVT::f32, Legal); in ARMTargetLowering()
1126 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in ARMTargetLowering()
1127 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal); in ARMTargetLowering()
1128 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal); in ARMTargetLowering()
1129 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal); in ARMTargetLowering()
1130 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal); in ARMTargetLowering()
1133 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); in ARMTargetLowering()
1134 setOperationAction(ISD::FCEIL, MVT::f64, Legal); in ARMTargetLowering()
1135 setOperationAction(ISD::FROUND, MVT::f64, Legal); in ARMTargetLowering()
1136 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); in ARMTargetLowering()
1137 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); in ARMTargetLowering()
1138 setOperationAction(ISD::FRINT, MVT::f64, Legal); in ARMTargetLowering()
1139 setOperationAction(ISD::FMINNUM, MVT::f64, Legal); in ARMTargetLowering()
1140 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in ARMTargetLowering()
1147 setOperationAction(ISD::FMINIMUM, MVT::f16, Legal); in ARMTargetLowering()
1148 setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal); in ARMTargetLowering()
1149 setOperationAction(ISD::FMINIMUM, MVT::f32, Legal); in ARMTargetLowering()
1150 setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal); in ARMTargetLowering()
1151 setOperationAction(ISD::FMINIMUM, MVT::v2f32, Legal); in ARMTargetLowering()
1152 setOperationAction(ISD::FMAXIMUM, MVT::v2f32, Legal); in ARMTargetLowering()
1153 setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal); in ARMTargetLowering()
1154 setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal); in ARMTargetLowering()
1157 setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal); in ARMTargetLowering()
1158 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal); in ARMTargetLowering()
1159 setOperationAction(ISD::FMINNUM, MVT::v8f16, Legal); in ARMTargetLowering()
1160 setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal); in ARMTargetLowering()
1162 setOperationAction(ISD::FMINIMUM, MVT::v4f16, Legal); in ARMTargetLowering()
1163 setOperationAction(ISD::FMAXIMUM, MVT::v4f16, Legal); in ARMTargetLowering()
1164 setOperationAction(ISD::FMINIMUM, MVT::v8f16, Legal); in ARMTargetLowering()
1165 setOperationAction(ISD::FMAXIMUM, MVT::v8f16, Legal); in ARMTargetLowering()
1225 MVT VT) const { in findRepresentativeClass()
1234 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16: in findRepresentativeClass()
1235 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32: in findRepresentativeClass()
1244 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: in findRepresentativeClass()
1245 case MVT::v4f32: case MVT::v2f64: in findRepresentativeClass()
1249 case MVT::v4i64: in findRepresentativeClass()
1253 case MVT::v8i64: in findRepresentativeClass()
1426 const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const { in getRegClassFor()
1431 if (VT == MVT::v4i64) in getRegClassFor()
1433 if (VT == MVT::v8i64) in getRegClassFor()
1467 if (VT == MVT::Glue || VT == MVT::Other) in getSchedulingPreference()
1688 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 && in LowerCallResult()
1697 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1702 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1708 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
1710 if (VA.getLocVT() == MVT::v2f64) { in LowerCallResult()
1711 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); in LowerCallResult()
1712 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
1713 DAG.getConstant(0, dl, MVT::i32)); in LowerCallResult()
1716 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1720 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1725 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
1726 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
1727 DAG.getConstant(1, dl, MVT::i32)); in LowerCallResult()
1773 DAG.getVTList(MVT::i32, MVT::i32), Arg); in PassF64ArgInRegs()
1889 if (VA.getLocVT() == MVT::v2f64) { in LowerCall()
1890 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, in LowerCall()
1891 DAG.getConstant(0, dl, MVT::i32)); in LowerCall()
1892 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, in LowerCall()
1893 DAG.getConstant(1, dl, MVT::i32)); in LowerCall()
1914 Outs[0].VT == MVT::i32) { in LowerCall()
1915 assert(VA.getLocVT() == MVT::i32 && in LowerCall()
1917 assert(!Ins.empty() && Ins[0].VT == MVT::i32 && in LowerCall()
1940 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32); in LowerCall()
1964 MVT::i32); in LowerCall()
1966 MVT::i32); in LowerCall()
1968 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); in LowerCall()
1982 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall()
2025 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); in LowerCall()
2039 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); in LowerCall()
2100 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); in LowerCall()
2104 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32); in LowerCall()
2164 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); in LowerCall()
2393 if (RegVT == MVT::v2f64) { in IsEligibleForTailCallOptimization()
2453 DAG.getConstant(LROffset, DL, MVT::i32, false)); in LowerInterruptReturn()
2455 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps); in LowerInterruptReturn()
2504 if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) { in LowerReturn()
2506 if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) { in LowerReturn()
2508 if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) { in LowerReturn()
2526 if (VA.getLocVT() == MVT::v2f64) { in LowerReturn()
2528 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, in LowerReturn()
2529 DAG.getConstant(0, dl, MVT::i32)); in LowerReturn()
2531 DAG.getVTList(MVT::i32, MVT::i32), Half); in LowerReturn()
2547 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, in LowerReturn()
2548 DAG.getConstant(1, dl, MVT::i32)); in LowerReturn()
2553 DAG.getVTList(MVT::i32, MVT::i32), Arg); in LowerReturn()
2570 ReturnF16 ? MVT::f16 : VA.getLocVT())); in LowerReturn()
2578 RetOps.push_back(DAG.getRegister(*I, MVT::i32)); in LowerReturn()
2580 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64))); in LowerReturn()
2604 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps); in LowerReturn()
2618 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue) in isUsedByReturnOnly()
2644 if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue) in isUsedByReturnOnly()
2659 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue) in isUsedByReturnOnly()
2701 assert(WriteValue.getValueType() == MVT::i64 in LowerWRITE_REGISTER()
2704 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue, in LowerWRITE_REGISTER()
2705 DAG.getConstant(0, DL, MVT::i32)); in LowerWRITE_REGISTER()
2706 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue, in LowerWRITE_REGISTER()
2707 DAG.getConstant(1, DL, MVT::i32)); in LowerWRITE_REGISTER()
2709 return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops); in LowerWRITE_REGISTER()
2753 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res); in LowerConstantPool()
2786 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32); in LowerBlockAddress()
2829 MVT::i32, DL, Chain, DescAddr, in LowerGlobalTLSAddressDarwin()
2853 DAG.getNode(ARMISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue), in LowerGlobalTLSAddressDarwin()
2854 Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32), in LowerGlobalTLSAddressDarwin()
2856 return DAG.getCopyFromReg(Chain, DL, ARM::R0, MVT::i32, Chain.getValue(1)); in LowerGlobalTLSAddressDarwin()
2870 DAG.getConstant(Intrinsic::arm_mrc, DL, MVT::i32), in LowerGlobalTLSAddressWindows()
2871 DAG.getConstant(15, DL, MVT::i32), in LowerGlobalTLSAddressWindows()
2872 DAG.getConstant(0, DL, MVT::i32), in LowerGlobalTLSAddressWindows()
2873 DAG.getConstant(13, DL, MVT::i32), in LowerGlobalTLSAddressWindows()
2874 DAG.getConstant(0, DL, MVT::i32), in LowerGlobalTLSAddressWindows()
2875 DAG.getConstant(2, DL, MVT::i32)}; in LowerGlobalTLSAddressWindows()
2877 DAG.getVTList(MVT::i32, MVT::Other), Ops); in LowerGlobalTLSAddressWindows()
2898 DAG.getConstant(2, DL, MVT::i32)); in LowerGlobalTLSAddressWindows()
2907 PtrVT, DL, Chain, DAG.getNode(ARMISD::Wrapper, DL, MVT::i32, in LowerGlobalTLSAddressWindows()
2928 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument); in LowerToTLSGeneralDynamicModel()
2934 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32); in LowerToTLSGeneralDynamicModel()
2979 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); in LowerToTLSExecModels()
2985 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32); in LowerToTLSExecModels()
2997 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); in LowerToTLSExecModels()
3150 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); in promoteToConstantPool()
3214 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); in LowerGlobalAddressELF()
3234 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); in LowerGlobalAddressELF()
3301 SDValue Val = DAG.getConstant(0, dl, MVT::i32); in LowerEH_SJLJ_SETJMP()
3303 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0), in LowerEH_SJLJ_SETJMP()
3310 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0), in LowerEH_SJLJ_LONGJMP()
3311 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32)); in LowerEH_SJLJ_LONGJMP()
3317 return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other, in LowerEH_SJLJ_SETUP_DISPATCH()
3344 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); in LowerINTRINSIC_WO_CHAIN()
3350 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32); in LowerINTRINSIC_WO_CHAIN()
3418 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0), in LowerATOMIC_FENCE()
3419 DAG.getConstant(0, dl, MVT::i32)); in LowerATOMIC_FENCE()
3436 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0), in LowerATOMIC_FENCE()
3437 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32), in LowerATOMIC_FENCE()
3438 DAG.getConstant(Domain, dl, MVT::i32)); in LowerATOMIC_FENCE()
3463 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0), in LowerPREFETCH()
3464 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32), in LowerPREFETCH()
3465 DAG.getConstant(isData, dl, MVT::i32)); in LowerPREFETCH()
3498 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); in GetF64FormalArgument()
3508 MVT::i32, dl, Root, FIN, in GetF64FormalArgument()
3512 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); in GetF64FormalArgument()
3516 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2); in GetF64FormalArgument()
3568 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); in StoreByValRegs()
3576 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); in StoreByValRegs()
3675 if (VA.getLocVT() == MVT::v2f64) { in LowerFormalArguments()
3683 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN, in LowerFormalArguments()
3690 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); in LowerFormalArguments()
3691 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, in LowerFormalArguments()
3694 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, in LowerFormalArguments()
3703 if (RegVT == MVT::f16) in LowerFormalArguments()
3705 else if (RegVT == MVT::f32) in LowerFormalArguments()
3707 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16) in LowerFormalArguments()
3709 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16) in LowerFormalArguments()
3711 else if (RegVT == MVT::i32) in LowerFormalArguments()
3747 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered"); in LowerFormalArguments()
3811 Op->getValueType(0) == MVT::f64) { in isFloatingPointZero()
3837 RHS = DAG.getConstant(C - 1, dl, MVT::i32); in getARMCmp()
3844 RHS = DAG.getConstant(C - 1, dl, MVT::i32); in getARMCmp()
3851 RHS = DAG.getConstant(C + 1, dl, MVT::i32); in getARMCmp()
3858 RHS = DAG.getConstant(C + 1, dl, MVT::i32); in getARMCmp()
3883 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32); in getARMCmp()
3884 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS); in getARMCmp()
3891 assert(!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64); in getVFPCmp()
3893 SDValue C = DAG.getConstant(InvalidOnQNaN, dl, MVT::i32); in getVFPCmp()
3895 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS, C); in getVFPCmp()
3897 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS, C); in getVFPCmp()
3898 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp); in getVFPCmp()
3908 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1)); in duplicateCmp()
3914 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0), in duplicateCmp()
3918 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0), in duplicateCmp()
3921 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp); in duplicateCmp()
3931 assert(Op.getValueType() == MVT::i32 && "Unsupported value type"); in getARMXALUOOp()
3947 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32); in getARMXALUOOp()
3949 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS); in getARMXALUOOp()
3952 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32); in getARMXALUOOp()
3956 DAG.getVTList(Op.getValueType(), MVT::i32), LHS, RHS) in getARMXALUOOp()
3958 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS); in getARMXALUOOp()
3961 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32); in getARMXALUOOp()
3963 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS); in getARMXALUOOp()
3966 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32); in getARMXALUOOp()
3968 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS); in getARMXALUOOp()
3972 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32); in getARMXALUOOp()
3976 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1), in getARMXALUOOp()
3977 DAG.getConstant(0, dl, MVT::i32)); in getARMXALUOOp()
3983 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32); in getARMXALUOOp()
3987 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1), in getARMXALUOOp()
3990 DAG.getConstant(31, dl, MVT::i32))); in getARMXALUOOp()
4007 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSignedALUO()
4010 SDValue TVal = DAG.getConstant(1, dl, MVT::i32); in LowerSignedALUO()
4011 SDValue FVal = DAG.getConstant(0, dl, MVT::i32); in LowerSignedALUO()
4017 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); in LowerSignedALUO()
4029 DAG.getVTList(CarryVT, MVT::i32), in ConvertBooleanCarryToCarryFlag()
4040 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32), in ConvertCarryFlagToBooleanCarry()
4041 DAG.getConstant(0, DL, MVT::i32), in ConvertCarryFlagToBooleanCarry()
4042 DAG.getConstant(0, DL, MVT::i32), Flags); in ConvertCarryFlagToBooleanCarry()
4056 SDVTList VTs = DAG.getVTList(VT, MVT::i32); in LowerUnsignedALUO()
4073 Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32, in LowerUnsignedALUO()
4074 DAG.getConstant(1, dl, MVT::i32), Overflow); in LowerUnsignedALUO()
4098 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT()
4203 if (Subtarget->isFPOnlySP() && VT == MVT::f64) { in getCMOV()
4205 DAG.getVTList(MVT::i32, MVT::i32), FalseVal); in getCMOV()
4207 DAG.getVTList(MVT::i32, MVT::i32), TrueVal); in getCMOV()
4214 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow, in getCMOV()
4216 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh, in getCMOV()
4219 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High); in getCMOV()
4434 if (VT == MVT::i32 && in LowerSELECT_CC()
4452 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) { in LowerSELECT_CC()
4453 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC, in LowerSELECT_CC()
4464 if (LHS.getValueType() == MVT::i32) { in LowerSELECT_CC()
4475 if (Subtarget->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 || in LowerSELECT_CC()
4476 TrueVal.getValueType() == MVT::f64)) { in LowerSELECT_CC()
4486 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC()
4498 (TrueVal.getValueType() == MVT::f16 || in LowerSELECT_CC()
4499 TrueVal.getValueType() == MVT::f32 || in LowerSELECT_CC()
4500 TrueVal.getValueType() == MVT::f64)) { in LowerSELECT_CC()
4514 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32); in LowerSELECT_CC()
4516 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC()
4519 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32); in LowerSELECT_CC()
4538 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow()) in canChangeToInt()
4552 return DAG.getConstant(0, SDLoc(Op), MVT::i32); in bitcastf32Toi32()
4555 return DAG.getLoad(MVT::i32, SDLoc(Op), Ld->getChain(), Ld->getBasePtr(), in bitcastf32Toi32()
4567 RetVal1 = DAG.getConstant(0, dl, MVT::i32); in expandf64Toi32()
4568 RetVal2 = DAG.getConstant(0, dl, MVT::i32); in expandf64Toi32()
4575 DAG.getLoad(MVT::i32, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(), in expandf64Toi32()
4582 RetVal2 = DAG.getLoad(MVT::i32, dl, Ld->getChain(), NewPtr, in expandf64Toi32()
4615 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32); in OptimizeVFPBrcond()
4617 if (LHS.getValueType() == MVT::f32) { in OptimizeVFPBrcond()
4618 LHS = DAG.getNode(ISD::AND, dl, MVT::i32, in OptimizeVFPBrcond()
4620 RHS = DAG.getNode(ISD::AND, dl, MVT::i32, in OptimizeVFPBrcond()
4623 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in OptimizeVFPBrcond()
4624 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, in OptimizeVFPBrcond()
4632 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask); in OptimizeVFPBrcond()
4633 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask); in OptimizeVFPBrcond()
4635 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32); in OptimizeVFPBrcond()
4636 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); in OptimizeVFPBrcond()
4671 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32); in LowerBRCOND()
4672 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBRCOND()
4674 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR, in LowerBRCOND()
4689 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) { in LowerBR_CC()
4690 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC, in LowerBR_CC()
4724 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32); in LowerBR_CC()
4726 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC()
4728 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR, in LowerBR_CC()
4732 if (LHS.getValueType() == MVT::i32) { in LowerBR_CC()
4735 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC()
4736 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, in LowerBR_CC()
4751 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32); in LowerBR_CC()
4753 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC()
4754 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); in LowerBR_CC()
4758 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32); in LowerBR_CC()
4774 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI); in LowerBR_JT()
4782 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain, in LowerBR_JT()
4787 DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr, in LowerBR_JT()
4791 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI); in LowerBR_JT()
4797 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI); in LowerBR_JT()
4805 if (Op.getValueType().getVectorElementType() == MVT::i32) { in LowerVectorFP_TO_INT()
4806 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32) in LowerVectorFP_TO_INT()
4816 if (OpTy == MVT::v4f32) in LowerVectorFP_TO_INT()
4817 NewTy = MVT::v4i32; in LowerVectorFP_TO_INT()
4818 else if (OpTy == MVT::v4f16 && HasFullFP16) in LowerVectorFP_TO_INT()
4819 NewTy = MVT::v4i16; in LowerVectorFP_TO_INT()
4820 else if (OpTy == MVT::v8f16 && HasFullFP16) in LowerVectorFP_TO_INT()
4821 NewTy = MVT::v8i16; in LowerVectorFP_TO_INT()
4825 if (VT != MVT::v4i16 && VT != MVT::v8i16) in LowerVectorFP_TO_INT()
4836 if (Subtarget->isFPOnlySP() && Op.getOperand(0).getValueType() == MVT::f64) { in LowerFP_TO_INT()
4855 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) { in LowerVectorINT_TO_FP()
4856 if (VT.getVectorElementType() == MVT::f32) in LowerVectorINT_TO_FP()
4861 assert((Op.getOperand(0).getValueType() == MVT::v4i16 || in LowerVectorINT_TO_FP()
4862 Op.getOperand(0).getValueType() == MVT::v8i16) && in LowerVectorINT_TO_FP()
4869 if (VT == MVT::v4f32) in LowerVectorINT_TO_FP()
4870 DestVecType = MVT::v4i32; in LowerVectorINT_TO_FP()
4871 else if (VT == MVT::v4f16 && HasFullFP16) in LowerVectorINT_TO_FP()
4872 DestVecType = MVT::v4i16; in LowerVectorINT_TO_FP()
4873 else if (VT == MVT::v8f16 && HasFullFP16) in LowerVectorINT_TO_FP()
4874 DestVecType = MVT::v8i16; in LowerVectorINT_TO_FP()
4900 if (Subtarget->isFPOnlySP() && Op.getValueType() == MVT::f64) { in LowerINT_TO_FP()
4929 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32, in LowerFCOPYSIGN()
4930 DAG.getTargetConstant(EncodedVal, dl, MVT::i32)); in LowerFCOPYSIGN()
4931 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64; in LowerFCOPYSIGN()
4932 if (VT == MVT::f64) in LowerFCOPYSIGN()
4935 DAG.getConstant(32, dl, MVT::i32)); in LowerFCOPYSIGN()
4937 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0); in LowerFCOPYSIGN()
4938 if (SrcVT == MVT::f32) { in LowerFCOPYSIGN()
4939 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1); in LowerFCOPYSIGN()
4940 if (VT == MVT::f64) in LowerFCOPYSIGN()
4943 DAG.getConstant(32, dl, MVT::i32)); in LowerFCOPYSIGN()
4944 } else if (VT == MVT::f32) in LowerFCOPYSIGN()
4945 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64, in LowerFCOPYSIGN()
4946 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1), in LowerFCOPYSIGN()
4947 DAG.getConstant(32, dl, MVT::i32)); in LowerFCOPYSIGN()
4952 dl, MVT::i32); in LowerFCOPYSIGN()
4953 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes); in LowerFCOPYSIGN()
4960 if (VT == MVT::f32) { in LowerFCOPYSIGN()
4961 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res); in LowerFCOPYSIGN()
4962 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res, in LowerFCOPYSIGN()
4963 DAG.getConstant(0, dl, MVT::i32)); in LowerFCOPYSIGN()
4965 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res); in LowerFCOPYSIGN()
4972 if (SrcVT == MVT::f64) in LowerFCOPYSIGN()
4973 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
4975 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1); in LowerFCOPYSIGN()
4978 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32); in LowerFCOPYSIGN()
4979 SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32); in LowerFCOPYSIGN()
4980 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1); in LowerFCOPYSIGN()
4981 if (VT == MVT::f32) { in LowerFCOPYSIGN()
4982 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32, in LowerFCOPYSIGN()
4983 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2); in LowerFCOPYSIGN()
4984 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, in LowerFCOPYSIGN()
4985 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1)); in LowerFCOPYSIGN()
4989 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
4992 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2); in LowerFCOPYSIGN()
4993 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1); in LowerFCOPYSIGN()
4994 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerFCOPYSIGN()
5010 SDValue Offset = DAG.getConstant(4, dl, MVT::i32); in LowerRETURNADDR()
5017 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32)); in LowerRETURNADDR()
5059 assert(N->getValueType(0) == MVT::i64 in ExpandREAD_REGISTER()
5063 DAG.getVTList(MVT::i32, MVT::i32, MVT::Other), in ExpandREAD_REGISTER()
5067 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Read.getValue(0), in ExpandREAD_REGISTER()
5119 DAG.getConstant(NewIndex.getZExtValue(), dl, MVT::i32)); in CombineVMOVDRRCandidateWithVecOp()
5139 if (SrcVT == MVT::f32 && DstVT == MVT::i32) { in ExpandBITCAST()
5147 Op.getValueType() != MVT::f32) in ExpandBITCAST()
5155 SDValue Copy = DAG.getNode(ISD::CopyFromReg, SDLoc(Op), MVT::f16, Ops); in ExpandBITCAST()
5160 if (SrcVT == MVT::i16 && DstVT == MVT::f16) { in ExpandBITCAST()
5169 if (Op.getOperand(0).getValueType() == MVT::i32) in ExpandBITCAST()
5171 MVT::f16, Op.getOperand(0)); in ExpandBITCAST()
5177 if (SrcVT == MVT::f16 && DstVT == MVT::i16) { in ExpandBITCAST()
5194 ZeroExtend->getValueType(0) != MVT::i32) in ExpandBITCAST()
5200 SDValue Cvt = DAG.getNode(ARMISD::VMOVrh, SDLoc(Op), MVT::i32, Op); in ExpandBITCAST()
5207 if (!(SrcVT == MVT::i64 || DstVT == MVT::i64)) in ExpandBITCAST()
5211 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) { in ExpandBITCAST()
5217 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, in ExpandBITCAST()
5218 DAG.getConstant(0, dl, MVT::i32)); in ExpandBITCAST()
5219 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, in ExpandBITCAST()
5220 DAG.getConstant(1, dl, MVT::i32)); in ExpandBITCAST()
5222 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi)); in ExpandBITCAST()
5226 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) { in ExpandBITCAST()
5231 DAG.getVTList(MVT::i32, MVT::i32), in ExpandBITCAST()
5235 DAG.getVTList(MVT::i32, MVT::i32), Op); in ExpandBITCAST()
5237 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); in ExpandBITCAST()
5252 SDValue EncodedVal = DAG.getTargetConstant(0, dl, MVT::i32); in getZeroVector()
5253 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32; in getZeroVector()
5270 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerShiftRightParts()
5275 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, in LowerShiftRightParts()
5276 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt); in LowerShiftRightParts()
5278 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, in LowerShiftRightParts()
5279 DAG.getConstant(VTBits, dl, MVT::i32)); in LowerShiftRightParts()
5283 SDValue CmpLo = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32), in LowerShiftRightParts()
5293 SDValue CmpHi = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32), in LowerShiftRightParts()
5314 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerShiftLeftParts()
5317 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, in LowerShiftLeftParts()
5318 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt); in LowerShiftLeftParts()
5323 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, in LowerShiftLeftParts()
5324 DAG.getConstant(VTBits, dl, MVT::i32)); in LowerShiftLeftParts()
5326 SDValue CmpHi = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32), in LowerShiftLeftParts()
5331 SDValue CmpLo = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32), in LowerShiftLeftParts()
5349 DAG.getConstant(Intrinsic::arm_get_fpscr, dl, MVT::i32) }; in LowerFLT_ROUNDS_()
5351 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_W_CHAIN, dl, MVT::i32, Ops); in LowerFLT_ROUNDS_()
5352 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR, in LowerFLT_ROUNDS_()
5353 DAG.getConstant(1U << 22, dl, MVT::i32)); in LowerFLT_ROUNDS_()
5354 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds, in LowerFLT_ROUNDS_()
5355 DAG.getConstant(22, dl, MVT::i32)); in LowerFLT_ROUNDS_()
5356 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE, in LowerFLT_ROUNDS_()
5357 DAG.getConstant(3, dl, MVT::i32)); in LowerFLT_ROUNDS_()
5374 if (ElemTy == MVT::i8) { in LowerCTTZ()
5382 if ((ElemTy == MVT::i16 || ElemTy == MVT::i32) && in LowerCTTZ()
5397 if (ElemTy == MVT::i64) { in LowerCTTZ()
5400 DAG.getTargetConstant(0x1eff, dl, MVT::i32)); in LowerCTTZ()
5423 assert((VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 || in LowerCTPOP()
5424 VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && in LowerCTPOP()
5428 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8; in LowerCTPOP()
5443 MVT WidenVT = MVT::getVectorVT(MVT::getIntegerVT(EltSize), NumElts); in LowerCTPOP()
5465 MVT::i32), in LowerShift()
5482 DAG.getConstant(vshiftInt, dl, MVT::i32), in LowerShift()
5492 if (VT != MVT::i64) in Expand64BitShift()
5506 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), in Expand64BitShift()
5507 DAG.getConstant(0, dl, MVT::i32)); in Expand64BitShift()
5508 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), in Expand64BitShift()
5509 DAG.getConstant(1, dl, MVT::i32)); in Expand64BitShift()
5514 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), Hi); in Expand64BitShift()
5517 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1)); in Expand64BitShift()
5520 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in Expand64BitShift()
5537 if (Op0.getValueType().getVectorElementType() == MVT::i64 && in LowerVSETCC()
5542 EVT SplitVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, CmpElements); in LowerVSETCC()
5556 if (CmpVT.getVectorElementType() == MVT::i64) in LowerVSETCC()
5692 Carry = DAG.getNode(ISD::SUB, DL, MVT::i32, in LowerSETCCCARRY()
5693 DAG.getConstant(1, DL, MVT::i32), Carry); in LowerSETCCCARRY()
5697 SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); in LowerSETCCCARRY()
5700 SDValue FVal = DAG.getConstant(0, DL, MVT::i32); in LowerSETCCCARRY()
5701 SDValue TVal = DAG.getConstant(1, DL, MVT::i32); in LowerSETCCCARRY()
5703 IntCCToARMCC(cast<CondCodeSDNode>(Cond)->get()), DL, MVT::i32); in LowerSETCCCARRY()
5704 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSETCCCARRY()
5736 VT = is128Bits ? MVT::v16i8 : MVT::v8i8; in isNEONModifiedImm()
5741 VT = is128Bits ? MVT::v8i16 : MVT::v4i16; in isNEONModifiedImm()
5761 VT = is128Bits ? MVT::v4i32 : MVT::v2i32; in isNEONModifiedImm()
5838 VT = is128Bits ? MVT::v2i64 : MVT::v1i64; in isNEONModifiedImm()
5847 return DAG.getTargetConstant(EncodedVal, dl, MVT::i32); in isNEONModifiedImm()
5853 bool IsDouble = (VT == MVT::f64); in LowerConstantFP()
5870 case MVT::f64: { in LowerConstantFP()
5871 SDValue Lo = DAG.getConstant(INTVal.trunc(32), DL, MVT::i32); in LowerConstantFP()
5872 SDValue Hi = DAG.getConstant(INTVal.lshr(32).trunc(32), DL, MVT::i32); in LowerConstantFP()
5875 return DAG.getNode(ARMISD::VMOVDRR, DL, MVT::f64, Lo, Hi); in LowerConstantFP()
5877 case MVT::f32: in LowerConstantFP()
5879 DAG.getConstant(INTVal, DL, MVT::i32)); in LowerConstantFP()
5904 SDValue NewVal = DAG.getTargetConstant(ImmVal, DL, MVT::i32); in LowerConstantFP()
5905 SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32, in LowerConstantFP()
5907 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant, in LowerConstantFP()
5908 DAG.getConstant(0, DL, MVT::i32)); in LowerConstantFP()
5933 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant); in LowerConstantFP()
5936 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32, in LowerConstantFP()
5938 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant, in LowerConstantFP()
5939 DAG.getConstant(0, DL, MVT::i32)); in LowerConstantFP()
5950 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant); in LowerConstantFP()
5953 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32, in LowerConstantFP()
5955 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant, in LowerConstantFP()
5956 DAG.getConstant(0, DL, MVT::i32)); in LowerConstantFP()
6061 return VT == MVT::v8i8 && M.size() == 8; in isVTBLMask()
6341 return DAG.getConstant(Val, dl, MVT::i32); in IsSingleInstrConstant()
6344 return DAG.getConstant(Val, dl, MVT::i32); in IsSingleInstrConstant()
6388 if ((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) { in LowerBUILD_VECTOR()
6391 SDValue Val = DAG.getTargetConstant(ImmVal, dl, MVT::i32); in LowerBUILD_VECTOR()
6471 Value, DAG.getConstant(index, dl, MVT::i32)), in LowerBUILD_VECTOR()
6472 DAG.getConstant(index, dl, MVT::i32)); in LowerBUILD_VECTOR()
6488 Ops.push_back(DAG.getConstant(I, dl, MVT::i32)); in LowerBUILD_VECTOR()
6497 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32, in LowerBUILD_VECTOR()
6499 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts); in LowerBUILD_VECTOR()
6525 if (VT.is128BitVector() && VT != MVT::v2f64 && VT != MVT::v4f32) { in LowerBUILD_VECTOR()
6570 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i32); in LowerBUILD_VECTOR()
6693 DAG.getConstant(NumSrcElts, dl, MVT::i32)); in ReconstructShuffle()
6699 DAG.getConstant(0, dl, MVT::i32)); in ReconstructShuffle()
6704 DAG.getConstant(0, dl, MVT::i32)); in ReconstructShuffle()
6707 DAG.getConstant(NumSrcElts, dl, MVT::i32)); in ReconstructShuffle()
6711 DAG.getConstant(Src.MinElt, dl, MVT::i32)); in ReconstructShuffle()
6817 ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(M, VT))); in isShuffleMaskLegal()
6862 if (VT.getVectorElementType() == MVT::i32 || in GeneratePerfectShuffle()
6863 VT.getVectorElementType() == MVT::f32) in GeneratePerfectShuffle()
6866 if (VT.getVectorElementType() == MVT::i16) in GeneratePerfectShuffle()
6869 assert(VT.getVectorElementType() == MVT::i8); in GeneratePerfectShuffle()
6876 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, dl, MVT::i32)); in GeneratePerfectShuffle()
6882 DAG.getConstant(OpNum - OP_VEXT1 + 1, dl, MVT::i32)); in GeneratePerfectShuffle()
6909 VTBLMask.push_back(DAG.getConstant(*I, DL, MVT::i32)); in LowerVECTOR_SHUFFLEv8i8()
6912 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1, in LowerVECTOR_SHUFFLEv8i8()
6913 DAG.getBuildVector(MVT::v8i8, DL, VTBLMask)); in LowerVECTOR_SHUFFLEv8i8()
6915 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2, in LowerVECTOR_SHUFFLEv8i8()
6916 DAG.getBuildVector(MVT::v8i8, DL, VTBLMask)); in LowerVECTOR_SHUFFLEv8i8()
6925 assert((VT == MVT::v8i16 || VT == MVT::v16i8) && in LowerReverse_VECTOR_SHUFFLEv16i8_v8i16()
6931 unsigned ExtractNum = (VT == MVT::v16i8) ? 8 : 4; in LowerReverse_VECTOR_SHUFFLEv16i8_v8i16()
6933 DAG.getConstant(ExtractNum, DL, MVT::i32)); in LowerReverse_VECTOR_SHUFFLEv16i8_v8i16()
6977 DAG.getConstant(Lane, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
6986 DAG.getConstant(Imm, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
6998 DAG.getConstant(Imm, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
7093 dl, MVT::i32))); in LowerVECTOR_SHUFFLE()
7099 if ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(ShuffleMask, VT)) in LowerVECTOR_SHUFFLE()
7102 if (VT == MVT::v8i8) in LowerVECTOR_SHUFFLE()
7125 if (Op.getValueType() == MVT::i32 && Vec.getScalarValueSizeInBits() < 32) { in LowerEXTRACT_VECTOR_ELT()
7127 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane); in LowerEXTRACT_VECTOR_ELT()
7139 SDValue Val = DAG.getUNDEF(MVT::v2f64); in LowerCONCAT_VECTORS()
7143 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, in LowerCONCAT_VECTORS()
7144 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0), in LowerCONCAT_VECTORS()
7147 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, in LowerCONCAT_VECTORS()
7148 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1), in LowerCONCAT_VECTORS()
7160 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) { in isExtendedBUILD_VECTOR()
7162 if (BVN->getValueType(0) != MVT::v4i32 || in isExtendedBUILD_VECTOR()
7233 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy; in getExtensionTo64Bits()
7236 case MVT::v2i8: in getExtensionTo64Bits()
7237 case MVT::v2i16: in getExtensionTo64Bits()
7238 return MVT::v2i32; in getExtensionTo64Bits()
7239 case MVT::v4i8: in getExtensionTo64Bits()
7240 return MVT::v4i16; in getExtensionTo64Bits()
7319 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR"); in SkipExtensionForVMULL()
7322 MVT::v2i32, SDLoc(N), in SkipExtensionForVMULL()
7330 MVT TruncVT = MVT::getIntegerVT(EltSize); in SkipExtensionForVMULL()
7338 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), dl, MVT::i32)); in SkipExtensionForVMULL()
7340 return DAG.getBuildVector(MVT::getVectorVT(TruncVT, NumElts), dl, Ops); in SkipExtensionForVMULL()
7401 if (VT == MVT::v2i64) in LowerMUL()
7447 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X); in LowerSDIV_v4i8()
7448 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y); in LowerSDIV_v4i8()
7449 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X); in LowerSDIV_v4i8()
7450 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y); in LowerSDIV_v4i8()
7453 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, in LowerSDIV_v4i8()
7454 DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32), in LowerSDIV_v4i8()
7460 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y); in LowerSDIV_v4i8()
7461 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X); in LowerSDIV_v4i8()
7462 Y = DAG.getConstant(0xb000, dl, MVT::v4i32); in LowerSDIV_v4i8()
7463 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y); in LowerSDIV_v4i8()
7464 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X); in LowerSDIV_v4i8()
7466 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X); in LowerSDIV_v4i8()
7467 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X); in LowerSDIV_v4i8()
7479 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
7480 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1); in LowerSDIV_v4i16()
7481 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); in LowerSDIV_v4i16()
7482 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1); in LowerSDIV_v4i16()
7487 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, in LowerSDIV_v4i16()
7488 DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32), in LowerSDIV_v4i16()
7490 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, in LowerSDIV_v4i16()
7491 DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32), in LowerSDIV_v4i16()
7493 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); in LowerSDIV_v4i16()
7498 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); in LowerSDIV_v4i16()
7499 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
7500 N1 = DAG.getConstant(0x89, dl, MVT::v4i32); in LowerSDIV_v4i16()
7501 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); in LowerSDIV_v4i16()
7502 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); in LowerSDIV_v4i16()
7505 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
7506 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); in LowerSDIV_v4i16()
7512 assert((VT == MVT::v4i16 || VT == MVT::v8i8) && in LowerSDIV()
7520 if (VT == MVT::v8i8) { in LowerSDIV()
7521 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0); in LowerSDIV()
7522 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1); in LowerSDIV()
7524 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
7526 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerSDIV()
7528 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
7530 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerSDIV()
7536 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerSDIV()
7539 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0); in LowerSDIV()
7548 assert((VT == MVT::v4i16 || VT == MVT::v8i8) && in LowerUDIV()
7556 if (VT == MVT::v8i8) { in LowerUDIV()
7557 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0); in LowerUDIV()
7558 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1); in LowerUDIV()
7560 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerUDIV()
7562 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerUDIV()
7564 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerUDIV()
7566 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerUDIV()
7572 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerUDIV()
7575 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8, in LowerUDIV()
7577 MVT::i32), in LowerUDIV()
7585 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0); in LowerUDIV()
7586 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1); in LowerUDIV()
7587 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); in LowerUDIV()
7588 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1); in LowerUDIV()
7594 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, in LowerUDIV()
7595 DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32), in LowerUDIV()
7597 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, in LowerUDIV()
7598 DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32), in LowerUDIV()
7600 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); in LowerUDIV()
7601 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, in LowerUDIV()
7602 DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32), in LowerUDIV()
7604 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); in LowerUDIV()
7609 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); in LowerUDIV()
7610 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); in LowerUDIV()
7611 N1 = DAG.getConstant(2, dl, MVT::v4i32); in LowerUDIV()
7612 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); in LowerUDIV()
7613 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); in LowerUDIV()
7616 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerUDIV()
7617 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); in LowerUDIV()
7624 SDVTList VTs = DAG.getVTList(VT, MVT::i32); in LowerADDSUBCARRY()
7644 Carry = DAG.getNode(ISD::SUB, DL, MVT::i32, in LowerADDSUBCARRY()
7645 DAG.getConstant(1, DL, MVT::i32), Carry); in LowerADDSUBCARRY()
7657 Carry = DAG.getNode(ISD::SUB, DL, MVT::i32, in LowerADDSUBCARRY()
7658 DAG.getConstant(1, DL, MVT::i32), Carry); in LowerADDSUBCARRY()
7711 (ArgVT == MVT::f64) ? RTLIB::SINCOS_STRET_F64 : RTLIB::SINCOS_STRET_F32; in LowerFSINCOS()
7744 assert((VT == MVT::i32 || VT == MVT::i64) && in LowerWindowsDIVLibCall()
7753 Name = (VT == MVT::i32) ? "__rt_sdiv" : "__rt_sdiv64"; in LowerWindowsDIVLibCall()
7755 Name = (VT == MVT::i32) ? "__rt_udiv" : "__rt_udiv64"; in LowerWindowsDIVLibCall()
7823 assert(Op.getValueType() == MVT::i32 && in LowerDIV_Windows()
7827 SDValue DBZCHK = DAG.getNode(ARMISD::WIN__DBZCHK, dl, MVT::Other, in LowerDIV_Windows()
7836 if (N->getValueType(0) == MVT::i32) in WinDBZCheckDenominator()
7837 return DAG.getNode(ARMISD::WIN__DBZCHK, DL, MVT::Other, InChain, Op); in WinDBZCheckDenominator()
7838 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Op, in WinDBZCheckDenominator()
7839 DAG.getConstant(0, DL, MVT::i32)); in WinDBZCheckDenominator()
7840 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Op, in WinDBZCheckDenominator()
7841 DAG.getConstant(1, DL, MVT::i32)); in WinDBZCheckDenominator()
7842 return DAG.getNode(ARMISD::WIN__DBZCHK, DL, MVT::Other, InChain, in WinDBZCheckDenominator()
7843 DAG.getNode(ISD::OR, DL, MVT::i32, Lo, Hi)); in WinDBZCheckDenominator()
7852 assert(Op.getValueType() == MVT::i64 && in ExpandDIV_Windows()
7860 SDValue Lower = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Result); in ExpandDIV_Windows()
7861 SDValue Upper = DAG.getNode(ISD::SRL, dl, MVT::i64, Result, in ExpandDIV_Windows()
7863 Upper = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Upper); in ExpandDIV_Windows()
7887 DAG.getConstant(Intrinsic::arm_mrc, DL, MVT::i32), in ReplaceREADCYCLECOUNTER()
7888 DAG.getConstant(15, DL, MVT::i32), in ReplaceREADCYCLECOUNTER()
7889 DAG.getConstant(0, DL, MVT::i32), in ReplaceREADCYCLECOUNTER()
7890 DAG.getConstant(9, DL, MVT::i32), in ReplaceREADCYCLECOUNTER()
7891 DAG.getConstant(13, DL, MVT::i32), in ReplaceREADCYCLECOUNTER()
7892 DAG.getConstant(0, DL, MVT::i32) in ReplaceREADCYCLECOUNTER()
7896 DAG.getVTList(MVT::i32, MVT::Other), Ops); in ReplaceREADCYCLECOUNTER()
7897 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Cycles32, in ReplaceREADCYCLECOUNTER()
7898 DAG.getConstant(0, DL, MVT::i32))); in ReplaceREADCYCLECOUNTER()
7904 SDValue VLo = DAG.getAnyExtOrTrunc(V, dl, MVT::i32); in createGPRPairNode()
7906 DAG.getNode(ISD::SRL, dl, MVT::i64, V, DAG.getConstant(32, dl, MVT::i32)), in createGPRPairNode()
7907 dl, MVT::i32); in createGPRPairNode()
7912 DAG.getTargetConstant(ARM::GPRPairRegClassID, dl, MVT::i32); in createGPRPairNode()
7913 SDValue SubReg0 = DAG.getTargetConstant(ARM::gsub_0, dl, MVT::i32); in createGPRPairNode()
7914 SDValue SubReg1 = DAG.getTargetConstant(ARM::gsub_1, dl, MVT::i32); in createGPRPairNode()
7917 DAG.getMachineNode(TargetOpcode::REG_SEQUENCE, dl, MVT::Untyped, Ops), 0); in createGPRPairNode()
7923 assert(N->getValueType(0) == MVT::i64 && in ReplaceCMP_SWAP_64Results()
7931 DAG.getVTList(MVT::Untyped, MVT::i32, MVT::Other), Ops); in ReplaceCMP_SWAP_64Results()
7940 SDLoc(N), MVT::i32, SDValue(CmpSwap, 0))); in ReplaceCMP_SWAP_64Results()
7943 SDLoc(N), MVT::i32, SDValue(CmpSwap, 0))); in ReplaceCMP_SWAP_64Results()
7956 MVT Ty = Val->getSimpleValueType(0); in LowerFPOWI()
7958 SDValue Callee = DAG.getExternalSymbol(Ty == MVT::f32 ? "powf" : "pow", in LowerFPOWI()
8098 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, in ReplaceLongIntrinsic()
8100 DAG.getConstant(0, dl, MVT::i32)); in ReplaceLongIntrinsic()
8101 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, in ReplaceLongIntrinsic()
8103 DAG.getConstant(1, dl, MVT::i32)); in ReplaceLongIntrinsic()
8106 DAG.getVTList(MVT::i32, MVT::i32), in ReplaceLongIntrinsic()
9690 if (CC.getValueType() != MVT::i1 || CC.getOpcode() != ISD::SETCC) in isConditionalZeroOrAllOnes()
9778 if (N->getOpcode() == ARMISD::VTRN && N->getValueType(0) == MVT::v2i32) in IsVUZPShuffleNode()
9877 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64) in AddCombineBUILD_VECTORToVPADDL()
9945 MVT widenType; in AddCombineBUILD_VECTORToVPADDL()
9950 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break; in AddCombineBUILD_VECTORToVPADDL()
9951 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break; in AddCombineBUILD_VECTORToVPADDL()
9952 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break; in AddCombineBUILD_VECTORToVPADDL()
10035 SDValue SMLAL = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), in AddCombineTo64BitSMLAL16()
10077 AddeSubeNode->getOperand(2).getValueType() == MVT::i32 && in AddCombineTo64bitMLAL()
10096 AddcSubcNode->getValueType(0) == MVT::i32 && in AddCombineTo64bitMLAL()
10188 SDValue NewNode = DAG.getNode(FinalOpc, SDLoc(AddcSubcNode), MVT::i32, Ops); in AddCombineTo64bitMLAL()
10202 DAG.getVTList(MVT::i32, MVT::i32), Ops); in AddCombineTo64bitMLAL()
10258 DAG.getVTList(MVT::i32, MVT::i32), Ops); in AddCombineTo64bitUMAAL()
10285 DAG.getVTList(MVT::i32, MVT::i32), in PerformUMLALCombine()
10314 RHS = DAG.getConstant(-imm, DL, MVT::i32); in PerformAddcSubcCombine()
10339 RHS = DAG.getConstant(~imm, DL, MVT::i32); in PerformAddeSubeCombine()
10516 SDValue BinOp = DAG.getNode(N->getOpcode(), dl, MVT::i32, X, in PerformSHLSimplify()
10517 DAG.getConstant(C1Int, dl, MVT::i32)); in PerformSHLSimplify()
10519 SDValue Res = DAG.getNode(ISD::SHL, dl, MVT::i32, BinOp, SHL.getOperand(1)); in PerformSHLSimplify()
10623 if (VT != MVT::i32) in PerformMULCombine()
10648 MVT::i32))); in PerformMULCombine()
10655 MVT::i32)), in PerformMULCombine()
10668 MVT::i32))); in PerformMULCombine()
10676 MVT::i32))); in PerformMULCombine()
10678 DAG.getConstant(0, DL, MVT::i32), Res); in PerformMULCombine()
10685 Res, DAG.getConstant(ShiftAmt, DL, MVT::i32)); in PerformMULCombine()
10699 if (N->getValueType(0) != MVT::i32) in CombineANDShift()
10746 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0), in CombineANDShift()
10747 DAG.getConstant(C3 - C2, DL, MVT::i32)); in CombineANDShift()
10748 return DAG.getNode(ISD::SRL, DL, MVT::i32, SHL, in CombineANDShift()
10749 DAG.getConstant(C3, DL, MVT::i32)); in CombineANDShift()
10757 SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0), in CombineANDShift()
10758 DAG.getConstant(C3 - C2, DL, MVT::i32)); in CombineANDShift()
10759 return DAG.getNode(ISD::SHL, DL, MVT::i32, SHL, in CombineANDShift()
10760 DAG.getConstant(C3, DL, MVT::i32)); in CombineANDShift()
10770 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0), in CombineANDShift()
10771 DAG.getConstant(C2 + C3, DL, MVT::i32)); in CombineANDShift()
10772 return DAG.getNode(ISD::SRL, DL, MVT::i32, SHL, in CombineANDShift()
10773 DAG.getConstant(C3, DL, MVT::i32)); in CombineANDShift()
10783 SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0), in CombineANDShift()
10784 DAG.getConstant(C2 + C3, DL, MVT::i32)); in CombineANDShift()
10785 return DAG.getNode(ISD::SHL, DL, MVT::i32, SHL, in CombineANDShift()
10786 DAG.getConstant(C3, DL, MVT::i32)); in CombineANDShift()
10900 SDValue Res = DAG.getNode(Opcode, dl, MVT::i32, OpS32, OpS16); in PerformORCombineToSMULWBT()
10927 if (VT != MVT::i32) in PerformORCombineToBFI()
10954 DAG.getConstant(Val, DL, MVT::i32), in PerformORCombineToBFI()
10955 DAG.getConstant(Mask, DL, MVT::i32)); in PerformORCombineToBFI()
10981 DAG.getConstant(amt, DL, MVT::i32)); in PerformORCombineToBFI()
10983 DAG.getConstant(Mask, DL, MVT::i32)); in PerformORCombineToBFI()
10998 DAG.getConstant(lsb, DL, MVT::i32)); in PerformORCombineToBFI()
11000 DAG.getConstant(Mask2, DL, MVT::i32)); in PerformORCombineToBFI()
11020 DAG.getConstant(~Mask, DL, MVT::i32)); in PerformORCombineToBFI()
11104 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32; in PerformORCombine()
11295 InNode->getValueType(0) == MVT::f64 && in PerformVMOVRRDCombine()
11305 DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr, LD->getPointerInfo(), in PerformVMOVRRDCombine()
11308 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, in PerformVMOVRRDCombine()
11309 DAG.getConstant(4, DL, MVT::i32)); in PerformVMOVRRDCombine()
11311 MVT::i32, DL, NewLD1.getValue(1), OffsetPtr, LD->getPointerInfo(), in PerformVMOVRRDCombine()
11373 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N)) in PerformBUILD_VECTORCombine()
11379 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i)); in PerformBUILD_VECTORCombine()
11384 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts); in PerformBUILD_VECTORCombine()
11412 assert(EltVT == MVT::f32 && "Unexpected type!"); in PerformARMBUILD_VECTORCombine()
11432 if (Elt->getOperand(0).getValueType() == MVT::i32) in PerformARMBUILD_VECTORCombine()
11446 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts); in PerformARMBUILD_VECTORCombine()
11464 V->getOperand(0).getValueType() == MVT::i32) in PerformARMBUILD_VECTORCombine()
11468 V = DAG.getNode(ISD::BITCAST, SDLoc(V), MVT::i32, V); in PerformARMBUILD_VECTORCombine()
11472 SDValue LaneIdx = DAG.getConstant(Idx, dl, MVT::i32); in PerformARMBUILD_VECTORCombine()
11489 if (VT.getVectorElementType() != MVT::i64 || in PerformInsertEltCombine()
11495 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, in PerformInsertEltCombine()
11498 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1)); in PerformInsertEltCombine()
11702 MVT EltTy = MVT::getIntegerVT(Alignment * 8); in CombineBaseUpdate()
11706 AlignedVecTy = MVT::getVectorVT(EltTy, NumElts); in CombineBaseUpdate()
11725 Tys[n++] = MVT::i32; in CombineBaseUpdate()
11726 Tys[n] = MVT::Other; in CombineBaseUpdate()
11746 Ops.push_back(DAG.getConstant(Alignment, dl, MVT::i32)); in CombineBaseUpdate()
11839 Tys[n] = MVT::Other; in CombineVLDDUP()
11914 DAG.getConstant(LD->getAlignment(), SDLoc(N), MVT::i32) }; in PerformVDUPCombine()
11915 SDVTList SDTys = DAG.getVTList(N->getValueType(0), MVT::Other); in PerformVDUPCombine()
11993 MVT StoreType = MVT::i8; in PerformSTORECombine()
11994 for (MVT Tp : MVT::integer_valuetypes()) { in PerformSTORECombine()
12025 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains); in PerformSTORECombine()
12044 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, in PerformSTORECombine()
12045 DAG.getConstant(4, DL, MVT::i32)); in PerformSTORECombine()
12053 if (StVal.getValueType() == MVT::i64 && in PerformSTORECombine()
12061 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, in PerformSTORECombine()
12064 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, in PerformSTORECombine()
12067 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt); in PerformSTORECombine()
12108 MVT FloatTy = Op.getSimpleValueType().getVectorElementType(); in PerformVCVTCombine()
12110 MVT IntTy = N->getSimpleValueType(0).getVectorElementType(); in PerformVCVTCombine()
12132 ISD::INTRINSIC_WO_CHAIN, dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32, in PerformVCVTCombine()
12133 DAG.getConstant(IntrinsicOpcode, dl, MVT::i32), Op->getOperand(0), in PerformVCVTCombine()
12134 DAG.getConstant(C, dl, MVT::i32)); in PerformVCVTCombine()
12166 MVT FloatTy = N->getSimpleValueType(0).getVectorElementType(); in PerformVDIVCombine()
12168 MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType(); in PerformVDIVCombine()
12190 dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32, in PerformVDIVCombine()
12197 DAG.getConstant(IntrinsicOpcode, dl, MVT::i32), in PerformVDIVCombine()
12198 ConvInput, DAG.getConstant(C, dl, MVT::i32)); in PerformVDIVCombine()
12365 N->getOperand(1), DAG.getConstant(Cnt, dl, MVT::i32)); in PerformIntrinsicCombine()
12384 DAG.getConstant(Cnt, dl, MVT::i32)); in PerformIntrinsicCombine()
12404 if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) { in PerformShiftCombine()
12432 DAG.getConstant(Cnt, dl, MVT::i32)); in PerformShiftCombine()
12443 DAG.getConstant(Cnt, dl, MVT::i32)); in PerformShiftCombine()
12466 if (VT == MVT::i32 && in PerformExtendCombine()
12467 (EltVT == MVT::i8 || EltVT == MVT::i16) && in PerformExtendCombine()
12707 DAG.getConstant(5, dl, MVT::i32)); in PerformCMOVCombine()
12719 SDVTList VTs = DAG.getVTList(VT, MVT::i32); in PerformCMOVCombine()
12724 DAG.getNode(ISD::SUB, dl, MVT::i32, in PerformCMOVCombine()
12725 DAG.getConstant(1, dl, MVT::i32), Neg.getValue(1)); in PerformCMOVCombine()
12733 DAG.getNode(ARMISD::SUBS, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS); in PerformCMOVCombine()
12747 DAG.getNode(ARMISD::SUBS, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS); in PerformCMOVCombine()
12751 DAG.getConstant(ARMCC::NE, dl, MVT::i32), in PerformCMOVCombine()
12770 SDVTList VTs = DAG.getVTList(VT, MVT::i32); in PerformCMOVCombine()
12778 ISD::SUB, dl, VT, DAG.getConstant(1, dl, MVT::i32), Res.getValue(1)); in PerformCMOVCombine()
12783 DAG.getConstant(ShiftAmount, dl, MVT::i32)); in PerformCMOVCombine()
12790 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, in PerformCMOVCombine()
12791 DAG.getValueType(MVT::i1)); in PerformCMOVCombine()
12793 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, in PerformCMOVCombine()
12794 DAG.getValueType(MVT::i8)); in PerformCMOVCombine()
12796 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, in PerformCMOVCombine()
12797 DAG.getValueType(MVT::i16)); in PerformCMOVCombine()
12935 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE); in isDesirableToTransformToIntegerOp()
12952 case MVT::i8: in allowsMisalignedMemoryAccesses()
12953 case MVT::i16: in allowsMisalignedMemoryAccesses()
12954 case MVT::i32: { in allowsMisalignedMemoryAccesses()
12963 case MVT::f64: in allowsMisalignedMemoryAccesses()
12964 case MVT::v2f64: { in allowsMisalignedMemoryAccesses()
12997 (allowsMisalignedMemoryAccesses(MVT::v2f64, 0, 1, &Fast) && Fast))) { in getOptimalMemOpType()
12998 return MVT::v2f64; in getOptimalMemOpType()
13001 (allowsMisalignedMemoryAccesses(MVT::f64, 0, 1, &Fast) && in getOptimalMemOpType()
13003 return MVT::f64; in getOptimalMemOpType()
13008 return MVT::Other; in getOptimalMemOpType()
13042 case MVT::i1: in isZExtFree()
13043 case MVT::i8: in isZExtFree()
13044 case MVT::i16: in isZExtFree()
13063 case MVT::f16: in isFNegFree()
13124 case MVT::i1: in isLegalT1AddressImmediate()
13125 case MVT::i8: in isLegalT1AddressImmediate()
13128 case MVT::i16: in isLegalT1AddressImmediate()
13132 case MVT::i32: in isLegalT1AddressImmediate()
13154 case MVT::i1: in isLegalT2AddressImmediate()
13155 case MVT::i8: in isLegalT2AddressImmediate()
13156 case MVT::i16: in isLegalT2AddressImmediate()
13157 case MVT::i32: in isLegalT2AddressImmediate()
13162 case MVT::f32: in isLegalT2AddressImmediate()
13163 case MVT::f64: in isLegalT2AddressImmediate()
13195 case MVT::i1: in isLegalAddressImmediate()
13196 case MVT::i8: in isLegalAddressImmediate()
13197 case MVT::i32: in isLegalAddressImmediate()
13200 case MVT::i16: in isLegalAddressImmediate()
13203 case MVT::f32: in isLegalAddressImmediate()
13204 case MVT::f64: in isLegalAddressImmediate()
13222 case MVT::i1: in isLegalT2ScaledAddressingMode()
13223 case MVT::i8: in isLegalT2ScaledAddressingMode()
13224 case MVT::i16: in isLegalT2ScaledAddressingMode()
13225 case MVT::i32: in isLegalT2ScaledAddressingMode()
13231 case MVT::i64: in isLegalT2ScaledAddressingMode()
13241 case MVT::isVoid: in isLegalT2ScaledAddressingMode()
13300 case MVT::i1: in isLegalAddressingMode()
13301 case MVT::i8: in isLegalAddressingMode()
13302 case MVT::i32: in isLegalAddressingMode()
13308 case MVT::i16: in isLegalAddressingMode()
13309 case MVT::i64: in isLegalAddressingMode()
13318 case MVT::isVoid: in isLegalAddressingMode()
13369 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { in getARMIndexedAddressParts()
13384 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) { in getARMIndexedAddressParts()
13511 assert(Op->getValueType(0) == MVT::i32 && "Non-i32 post-inc op?!"); in getPostIndexedAddressParts()
13663 assert(VT == MVT::i32 && "Unexpected integer type"); in targetShrinkDemandedConstant()
13847 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const { in getRegForInlineAsmConstraint()
13864 if (VT == MVT::Other) in getRegForInlineAsmConstraint()
13866 if (VT == MVT::f32) in getRegForInlineAsmConstraint()
13874 if (VT == MVT::Other) in getRegForInlineAsmConstraint()
13876 if (VT == MVT::f32) in getRegForInlineAsmConstraint()
13884 if (VT == MVT::Other) in getRegForInlineAsmConstraint()
13886 if (VT == MVT::f32 || VT == MVT::i32) in getRegForInlineAsmConstraint()
14069 const SDNode *N, MVT::SimpleValueType SVT) { in getDivRemLibcall()
14078 case MVT::i8: LC = isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break; in getDivRemLibcall()
14079 case MVT::i16: LC = isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break; in getDivRemLibcall()
14080 case MVT::i32: LC = isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break; in getDivRemLibcall()
14081 case MVT::i64: LC = isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break; in getDivRemLibcall()
14130 Op->getSimpleValueType(0) == MVT::i32) { in LowerDivRem()
14176 case MVT::i8: RetTyElement = Type::getInt8Ty(*DAG.getContext()); break; in LowerREM()
14177 case MVT::i16: RetTyElement = Type::getInt16Ty(*DAG.getContext()); break; in LowerREM()
14178 case MVT::i32: RetTyElement = Type::getInt32Ty(*DAG.getContext()); break; in LowerREM()
14179 case MVT::i64: RetTyElement = Type::getInt64Ty(*DAG.getContext()); break; in LowerREM()
14224 SDValue SP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32); in LowerDYNAMIC_STACKALLOC()
14226 SP = DAG.getNode(ISD::SUB, DL, MVT::i32, SP, Size); in LowerDYNAMIC_STACKALLOC()
14228 SP = DAG.getNode(ISD::AND, DL, MVT::i32, SP.getValue(0), in LowerDYNAMIC_STACKALLOC()
14229 DAG.getConstant(-(uint64_t)Align, DL, MVT::i32)); in LowerDYNAMIC_STACKALLOC()
14235 SDValue Words = DAG.getNode(ISD::SRL, DL, MVT::i32, Size, in LowerDYNAMIC_STACKALLOC()
14236 DAG.getConstant(2, DL, MVT::i32)); in LowerDYNAMIC_STACKALLOC()
14242 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); in LowerDYNAMIC_STACKALLOC()
14245 SDValue NewSP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32); in LowerDYNAMIC_STACKALLOC()
14253 assert(Op.getValueType() == MVT::f64 && Subtarget->isFPOnlySP() && in LowerFP_EXTEND()
14265 assert(Op.getOperand(0).getValueType() == MVT::f64 && in LowerFP_ROUND()
14298 if (VT == MVT::f16 && Subtarget->hasFullFP16()) in isFPImmLegal()
14300 if (VT == MVT::f32) in isFPImmLegal()
14302 if (VT == MVT::f64 && !Subtarget->isFPOnlySP()) in isFPImmLegal()
14329 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); in getTgtMemIntrinsic()
14345 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); in getTgtMemIntrinsic()
14370 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); in getTgtMemIntrinsic()
14392 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); in getTgtMemIntrinsic()
14405 Info.memVT = MVT::getVT(PtrTy->getElementType()); in getTgtMemIntrinsic()
14417 Info.memVT = MVT::getVT(PtrTy->getElementType()); in getTgtMemIntrinsic()
14427 Info.memVT = MVT::i64; in getTgtMemIntrinsic()
14437 Info.memVT = MVT::i64; in getTgtMemIntrinsic()