245                         bool is64BitVector);
1602                                        unsigned NumVecs, bool is64BitVector) {  in GetVLDSTAlign()  argument
1604   if (!is64BitVector && NumVecs < 3)  in GetVLDSTAlign()
1758   bool is64BitVector = VT.is64BitVector();  in SelectVLD()  local
1759   Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);  in SelectVLD()
1786     if (!is64BitVector)  in SelectVLD()
1802   if (is64BitVector || NumVecs <= 2) {  in SelectVLD()
1803     unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :  in SelectVLD()
1871   unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);  in SelectVLD()
1900   bool is64BitVector = VT.is64BitVector();  in SelectVST()  local
1901   Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);  in SelectVST()
1933   if (is64BitVector || NumVecs <= 2) {  in SelectVST()
1937     } else if (is64BitVector) {  in SelectVST()
1959     unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :  in SelectVST()
2053   bool is64BitVector = VT.is64BitVector();  in SelectVLDSTLane()  local
2087     if (!is64BitVector)  in SelectVLDSTLane()
2113     if (is64BitVector)  in SelectVLDSTLane()
2122     if (is64BitVector)  in SelectVLDSTLane()
2133   unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :  in SelectVLDSTLane()
2147   unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;  in SelectVLDSTLane()
2172   bool is64BitVector = VT.is64BitVector();  in SelectVLDDup()  local
2205   if (!is64BitVector)  in SelectVLDDup()
2219   if (is64BitVector || NumVecs == 1) {  in SelectVLDDup()
2223     unsigned Opc = is64BitVector ? DOpcodes[OpcodeIndex] :  in SelectVLDDup()
2274     unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;  in SelectVLDDup()