Lines Matching refs:Ops
1408 SDValue Ops[]= { Base, AMOpc, getAL(CurDAG, SDLoc(N)), in tryARMIndexedLoad() local
1411 MVT::Other, Ops); in tryARMIndexedLoad()
1418 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG, SDLoc(N)), in tryARMIndexedLoad() local
1421 MVT::Other, Ops); in tryARMIndexedLoad()
1449 SDValue Ops[]= { Base, getAL(CurDAG, SDLoc(N)), in tryT1IndexedLoad() local
1452 MVT::i32, MVT::Other, Ops); in tryT1IndexedLoad()
1497 SDValue Ops[]= { Base, Offset, getAL(CurDAG, SDLoc(N)), in tryT2IndexedLoad() local
1500 MVT::Other, Ops); in tryT2IndexedLoad()
1516 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createGPRPairNode() local
1517 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createGPRPairNode()
1527 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createSRegPairNode() local
1528 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createSRegPairNode()
1538 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createDRegPairNode() local
1539 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createDRegPairNode()
1549 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createQRegPairNode() local
1550 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createQRegPairNode()
1563 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadSRegsNode() local
1565 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createQuadSRegsNode()
1578 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadDRegsNode() local
1580 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createQuadDRegsNode()
1593 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadQRegsNode() local
1595 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops); in createQuadQRegsNode()
1799 SmallVector<SDValue, 7> Ops; in SelectVLD() local
1805 Ops.push_back(MemAddr); in SelectVLD()
1806 Ops.push_back(Align); in SelectVLD()
1815 Ops.push_back(Inc); in SelectVLD()
1819 Ops.push_back(Reg0); in SelectVLD()
1821 Ops.push_back(Pred); in SelectVLD()
1822 Ops.push_back(Reg0); in SelectVLD()
1823 Ops.push_back(Chain); in SelectVLD()
1824 VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops); in SelectVLD()
1841 Ops.push_back(SDValue(VLdA, 1)); in SelectVLD()
1842 Ops.push_back(Align); in SelectVLD()
1848 Ops.push_back(Reg0); in SelectVLD()
1850 Ops.push_back(SDValue(VLdA, 0)); in SelectVLD()
1851 Ops.push_back(Pred); in SelectVLD()
1852 Ops.push_back(Reg0); in SelectVLD()
1853 Ops.push_back(Chain); in SelectVLD()
1854 VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys, Ops); in SelectVLD()
1930 SmallVector<SDValue, 7> Ops; in SelectVST() local
1961 Ops.push_back(MemAddr); in SelectVST()
1962 Ops.push_back(Align); in SelectVST()
1971 Ops.push_back(Inc); in SelectVST()
1976 Ops.push_back(Reg0); in SelectVST()
1978 Ops.push_back(SrcReg); in SelectVST()
1979 Ops.push_back(Pred); in SelectVST()
1980 Ops.push_back(Reg0); in SelectVST()
1981 Ops.push_back(Chain); in SelectVST()
1982 SDNode *VSt = CurDAG->getMachineNode(Opc, dl, ResTys, Ops); in SelectVST()
2013 Ops.push_back(SDValue(VStA, 0)); in SelectVST()
2014 Ops.push_back(Align); in SelectVST()
2020 Ops.push_back(Reg0); in SelectVST()
2022 Ops.push_back(RegSeq); in SelectVST()
2023 Ops.push_back(Pred); in SelectVST()
2024 Ops.push_back(Reg0); in SelectVST()
2025 Ops.push_back(Chain); in SelectVST()
2027 Ops); in SelectVST()
2099 SmallVector<SDValue, 8> Ops; in SelectVLDSTLane() local
2100 Ops.push_back(MemAddr); in SelectVLDSTLane()
2101 Ops.push_back(Align); in SelectVLDSTLane()
2106 Ops.push_back(IsImmUpdate ? Reg0 : Inc); in SelectVLDSTLane()
2127 Ops.push_back(SuperReg); in SelectVLDSTLane()
2128 Ops.push_back(getI32Imm(Lane, dl)); in SelectVLDSTLane()
2129 Ops.push_back(Pred); in SelectVLDSTLane()
2130 Ops.push_back(Reg0); in SelectVLDSTLane()
2131 Ops.push_back(Chain); in SelectVLDSTLane()
2135 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops); in SelectVLDSTLane()
2220 SmallVector<SDValue, 6> Ops; in SelectVLDDup() local
2221 Ops.push_back(MemAddr); in SelectVLDDup()
2222 Ops.push_back(Align); in SelectVLDDup()
2234 Ops.push_back(Inc); in SelectVLDDup()
2237 Ops.push_back(Reg0); in SelectVLDDup()
2239 Ops.push_back(Pred); in SelectVLDDup()
2240 Ops.push_back(Reg0); in SelectVLDDup()
2241 Ops.push_back(Chain); in SelectVLDDup()
2242 VLdDup = CurDAG->getMachineNode(Opc, dl, ResTys, Ops); in SelectVLDDup()
2324 SDValue Ops[] = { N->getOperand(0).getOperand(0), in tryV6T2BitfieldExtractOp() local
2327 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in tryV6T2BitfieldExtractOp()
2336 SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc, in tryV6T2BitfieldExtractOp() local
2338 CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops); in tryV6T2BitfieldExtractOp()
2343 SDValue Ops[] = { N->getOperand(0).getOperand(0), in tryV6T2BitfieldExtractOp() local
2347 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in tryV6T2BitfieldExtractOp()
2368 SDValue Ops[] = { N->getOperand(0).getOperand(0), in tryV6T2BitfieldExtractOp() local
2372 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in tryV6T2BitfieldExtractOp()
2390 SDValue Ops[] = { N->getOperand(0).getOperand(0), in tryV6T2BitfieldExtractOp() local
2394 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in tryV6T2BitfieldExtractOp()
2411 SDValue Ops[] = { N->getOperand(0).getOperand(0), in tryV6T2BitfieldExtractOp() local
2415 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in tryV6T2BitfieldExtractOp()
2475 SDValue Ops[] = {N->getOperand(1), N->getOperand(2), N->getOperand(3), in SelectCMP_SWAP() local
2479 CurDAG->getVTList(MVT::i32, MVT::i32, MVT::Other), Ops); in SelectCMP_SWAP()
2532 SDValue Ops[] = { Src, CurDAG->getTargetConstant(Imm, dl, MVT::i32), in SelectCMPZ() local
2535 return CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops); in SelectCMPZ()
2537 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), Src, in SelectCMPZ() local
2540 return CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops); in SelectCMPZ()
2608 SDValue Ops[] = { in Select() local
2615 Ops); in Select()
2617 SDValue Ops[] = { in Select() local
2625 Ops); in Select()
2661 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, dl, MVT::i32), in Select() local
2664 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops); in Select()
2692 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 }; in Select() local
2693 CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops); in Select()
2696 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0, in Select() local
2698 CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops); in Select()
2711 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 }; in Select() local
2712 CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops); in Select()
2715 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0, in Select() local
2717 CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops); in Select()
2754 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), in Select() local
2757 ReplaceNode(N, CurDAG->getMachineNode(ARM::tBIC, dl, MVT::i32, Ops)); in Select()
2760 SDValue Ops[] = {N->getOperand(0), NewImm, getAL(CurDAG, dl), in Select() local
2764 CurDAG->getMachineNode(ARM::t2BICrr, dl, MVT::i32, Ops)); in Select()
2799 SDValue Ops[] = { N0.getOperand(0), Imm16, in Select() local
2801 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, Ops)); in Select()
2810 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select() local
2814 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, MVT::i32, MVT::i32, Ops)); in Select()
2819 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), in Select() local
2823 N, CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops)); in Select()
2826 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), in Select() local
2832 MVT::i32, MVT::i32, Ops)); in Select()
2838 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), in Select() local
2842 N, CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops)); in Select()
2845 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), in Select() local
2851 MVT::i32, MVT::i32, Ops)); in Select()
2880 SDValue Ops[] = { SmulLoHi.getOperand(0), SmulLoHi.getOperand(1), in Select() local
2883 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops)); in Select()
2943 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag }; in Select() local
2945 MVT::Glue, Ops); in Select()
2974 SDValue Ops[] = { X, CurDAG->getTargetConstant(Addend, dl, MVT::i32), in Select() local
2977 Add = CurDAG->getMachineNode(ARM::t2ADDri, dl, MVT::i32, Ops); in Select()
2980 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), X, in Select() local
2983 Add = CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops); in Select()
3017 SDValue Ops[] = {N->getOperand(0), N->getOperand(1), NewARMcc, in Select() local
3019 CurDAG->MorphNodeTo(N, ARMISD::CMOV, N->getVTList(), Ops); in Select()
3046 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select() local
3047 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, VT, Ops)); in Select()
3069 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select() local
3070 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, VT, Ops)); in Select()
3091 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select() local
3092 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, VT, Ops)); in Select()
3373 SmallVector<SDValue, 5> Ops; in Select() local
3374 … Ops.push_back(getI32Imm(cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(), dl)); /* coproc */ in Select()
3375 … Ops.push_back(getI32Imm(cast<ConstantSDNode>(N->getOperand(3))->getZExtValue(), dl)); /* opc */ in Select()
3376 … Ops.push_back(getI32Imm(cast<ConstantSDNode>(N->getOperand(4))->getZExtValue(), dl)); /* CRm */ in Select()
3382 Ops.push_back(getAL(CurDAG, dl)); in Select()
3383 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); in Select()
3386 Ops.push_back(Chain); in Select()
3391 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, RetType, Ops)); in Select()
3415 SDValue Ops[] = {MemAddr, getAL(CurDAG, dl), in Select() local
3417 SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops); in Select()
3468 SmallVector<SDValue, 7> Ops; in Select() local
3470 Ops.push_back(Val0); in Select()
3471 Ops.push_back(Val1); in Select()
3474 Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, Val0, Val1), 0)); in Select()
3475 Ops.push_back(MemAddr); in Select()
3476 Ops.push_back(getAL(CurDAG, dl)); in Select()
3477 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); in Select()
3478 Ops.push_back(Chain); in Select()
3484 SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops); in Select()
3804 std::vector<SDValue> &Ops) { in getIntOperandsFromRegisterString() argument
3815 Ops.push_back(CurDAG->getTargetConstant(IntField, DL, MVT::i32)); in getIntOperandsFromRegisterString()
3926 std::vector<SDValue> Ops; in tryReadRegister() local
3927 getIntOperandsFromRegisterString(RegString->getString(), CurDAG, DL, Ops); in tryReadRegister()
3929 if (!Ops.empty()) { in tryReadRegister()
3936 if (Ops.size() == 5){ in tryReadRegister()
3940 assert(Ops.size() == 3 && in tryReadRegister()
3946 Ops.push_back(getAL(CurDAG, DL)); in tryReadRegister()
3947 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); in tryReadRegister()
3948 Ops.push_back(N->getOperand(0)); in tryReadRegister()
3949 ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, ResTypes, Ops)); in tryReadRegister()
3957 Ops = { CurDAG->getTargetConstant(BankedReg, DL, MVT::i32), in tryReadRegister()
3962 DL, MVT::i32, MVT::Other, Ops)); in tryReadRegister()
3987 Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32), in tryReadRegister()
3990 CurDAG->getMachineNode(Opcode, DL, MVT::i32, MVT::Other, Ops)); in tryReadRegister()
4002 SDValue Ops[] = { CurDAG->getTargetConstant(SYSmValue, DL, MVT::i32), in tryReadRegister() local
4006 N, CurDAG->getMachineNode(ARM::t2MRS_M, DL, MVT::i32, MVT::Other, Ops)); in tryReadRegister()
4013 Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32), in tryReadRegister()
4016 DL, MVT::i32, MVT::Other, Ops)); in tryReadRegister()
4021 Ops = { getAL(CurDAG, DL), CurDAG->getRegister(0, MVT::i32), in tryReadRegister()
4025 MVT::i32, MVT::Other, Ops)); in tryReadRegister()
4041 std::vector<SDValue> Ops; in tryWriteRegister() local
4042 getIntOperandsFromRegisterString(RegString->getString(), CurDAG, DL, Ops); in tryWriteRegister()
4044 if (!Ops.empty()) { in tryWriteRegister()
4050 if (Ops.size() == 5) { in tryWriteRegister()
4052 Ops.insert(Ops.begin()+2, N->getOperand(2)); in tryWriteRegister()
4054 assert(Ops.size() == 3 && in tryWriteRegister()
4058 Ops.insert(Ops.begin()+2, WriteValue, WriteValue+2); in tryWriteRegister()
4061 Ops.push_back(getAL(CurDAG, DL)); in tryWriteRegister()
4062 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); in tryWriteRegister()
4063 Ops.push_back(N->getOperand(0)); in tryWriteRegister()
4065 ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops)); in tryWriteRegister()
4072 Ops = { CurDAG->getTargetConstant(BankedReg, DL, MVT::i32), N->getOperand(2), in tryWriteRegister()
4077 DL, MVT::Other, Ops)); in tryWriteRegister()
4095 Ops = { N->getOperand(2), getAL(CurDAG, DL), in tryWriteRegister()
4097 ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops)); in tryWriteRegister()
4113 SDValue Ops[] = { CurDAG->getTargetConstant(SYSmValue, DL, MVT::i32), in tryWriteRegister() local
4116 ReplaceNode(N, CurDAG->getMachineNode(ARM::t2MSR_M, DL, MVT::Other, Ops)); in tryWriteRegister()
4125 Ops = { CurDAG->getTargetConstant(Mask, DL, MVT::i32), N->getOperand(2), in tryWriteRegister()
4129 DL, MVT::Other, Ops)); in tryWriteRegister()
4243 std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1); in tryInlineAsm() local
4244 Ops.push_back(T1.getValue(1)); in tryInlineAsm()
4245 CurDAG->UpdateNodeOperands(GU, Ops); in tryInlineAsm()