195                     bool isZExt, bool isEquality);
197                      unsigned Alignment = 0, bool isZExt = true,
206     unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
920                               unsigned Alignment, bool isZExt, bool allocReg) {  in ARMEmitLoad()  argument
932           Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;  in ARMEmitLoad()
934           Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;  in ARMEmitLoad()
936         if (isZExt) {  in ARMEmitLoad()
951           Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;  in ARMEmitLoad()
953           Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;  in ARMEmitLoad()
955         Opc = isZExt ? ARM::LDRH : ARM::LDRSH;  in ARMEmitLoad()
1353                              bool isZExt, bool isEquality) {  in ARMEmitCmp()  argument
1376       Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();  in ARMEmitCmp()
1446     SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);  in ARMEmitCmp()
1449       SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);  in ARMEmitCmp()
2159       if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {  in SelectRet()
2160         SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());  in SelectRet()
2611                                     bool isZExt) {  in ARMEmitIntExt()  argument
2696   bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt];  in ARMEmitIntExt()
2698   const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt];  in ARMEmitIntExt()
2756   bool isZExt = isa<ZExtInst>(I);  in SelectIntExt()  local
2768   unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);  in SelectIntExt()
2906   uint8_t isZExt     : 1;  member
2936   bool isZExt;  in tryToFoldLoadIntoMI()  local
2942       isZExt = FLE.isZExt;  in tryToFoldLoadIntoMI()
2952   if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))  in tryToFoldLoadIntoMI()