498     MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
502     MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
504       MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
506       MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
508       MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));  in ExpandVLD()
569   MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));  in ExpandVLD()
687     MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
689       MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
691       MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
693       MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));  in ExpandLaneOp()
735     MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));  in ExpandLaneOp()
842       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMOV32BitImm()
874     .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMOV32BitImm()
1447               .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
1502             .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
1543         .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
1594       MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
1595         .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));  in ExpandMI()
1598       MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));  in ExpandMI()