Lines Matching refs:RegSpc
436 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, in GetDSubRegs() argument
439 if (RegSpc == SingleSpc || RegSpc == SingleLowSpc) { in GetDSubRegs()
444 } else if (RegSpc == SingleHighQSpc) { in GetDSubRegs()
449 } else if (RegSpc == SingleHighTSpc) { in GetDSubRegs()
454 } else if (RegSpc == EvenDblSpc) { in GetDSubRegs()
460 assert(RegSpc == OddDblSpc && "unknown register spacing"); in GetDSubRegs()
476 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; in ExpandVLD() local
489 if (RegSpc == EvenDblSpc) { in ExpandVLD()
492 assert(RegSpc == OddDblSpc && "Unexpected spacing!"); in ExpandVLD()
501 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); in ExpandVLD()
551 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc || in ExpandVLD()
552 RegSpc == SingleLowSpc || RegSpc == SingleHighQSpc || in ExpandVLD()
553 RegSpc == SingleHighTSpc) in ExpandVLD()
586 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; in ExpandVST() local
628 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3); in ExpandVST()
661 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; in ExpandLaneOp() local
673 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane"); in ExpandLaneOp()
674 if (RegSpc == EvenDblSpc && Lane >= RegElts) { in ExpandLaneOp()
675 RegSpc = OddDblSpc; in ExpandLaneOp()
686 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); in ExpandLaneOp()
709 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3); in ExpandLaneOp()