66 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {  in getCalleeSavedRegs()
67   const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();  in getCalleeSavedRegs()
68   bool UseSplitPush = STI.splitFramePushPop(*MF);  in getCalleeSavedRegs()
74   const Function &F = MF->getFunction();  in getCalleeSavedRegs()
105     return MF->getInfo<ARMFunctionInfo>()->isSplitCSR()  in getCalleeSavedRegs()
112     const MachineFunction *MF) const {  in getCalleeSavedRegsViaCopy()
113   assert(MF && "Invalid MachineFunction pointer.");  in getCalleeSavedRegsViaCopy()
114   if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&  in getCalleeSavedRegsViaCopy()
115       MF->getInfo<ARMFunctionInfo>()->isSplitCSR())  in getCalleeSavedRegsViaCopy()
121 ARMBaseRegisterInfo::getCallPreservedMask(const MachineFunction &MF,  in getCallPreservedMask()  argument
123   const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();  in getCallPreservedMask()
129       MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))  in getCallPreservedMask()
144 ARMBaseRegisterInfo::getTLSCallPreservedMask(const MachineFunction &MF) const {  in getTLSCallPreservedMask()
145   assert(MF.getSubtarget<ARMSubtarget>().isTargetDarwin() &&  in getTLSCallPreservedMask()
151 ARMBaseRegisterInfo::getSjLjDispatchPreservedMask(const MachineFunction &MF) const {  in getSjLjDispatchPreservedMask()
152   const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();  in getSjLjDispatchPreservedMask()
160 ARMBaseRegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,  in getThisReturnPreservedMask()  argument
162   const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();  in getThisReturnPreservedMask()
179 getReservedRegs(const MachineFunction &MF) const {  in getReservedRegs()
180   const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();  in getReservedRegs()
181   const ARMFrameLowering *TFI = getFrameLowering(MF);  in getReservedRegs()
189   if (TFI->hasFP(MF))  in getReservedRegs()
191   if (hasBasePointer(MF))  in getReservedRegs()
213 isAsmClobberable(const MachineFunction &MF, unsigned PhysReg) const {  in isAsmClobberable()  argument
214   return !getReservedRegs(MF).test(PhysReg);  in isAsmClobberable()
239 ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)  in getPointerRegClass()  argument
253                                          MachineFunction &MF) const {  in getRegPressureLimit()
254   const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();  in getRegPressureLimit()
255   const ARMFrameLowering *TFI = getFrameLowering(MF);  in getRegPressureLimit()
264     bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()  in getRegPressureLimit()
265                  ? TFI->hasFP(MF) : true;  in getRegPressureLimit()
269     bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()  in getRegPressureLimit()
270                  ? TFI->hasFP(MF) : true;  in getRegPressureLimit()
292                                            const MachineFunction &MF,  in getRegAllocationHints()  argument
295   const MachineRegisterInfo &MRI = MF.getRegInfo();  in getRegAllocationHints()
307     TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);  in getRegAllocationHints()
344                                         MachineFunction &MF) const {  in updateRegAllocHint()
345   MachineRegisterInfo *MRI = &MF.getRegInfo();  in updateRegAllocHint()
367 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {  in hasBasePointer()
368   const MachineFrameInfo &MFI = MF.getFrameInfo();  in hasBasePointer()
369   const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();  in hasBasePointer()
370   const ARMFrameLowering *TFI = getFrameLowering(MF);  in hasBasePointer()
375   if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))  in hasBasePointer()
398 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {  in canRealignStack()
399   const MachineRegisterInfo *MRI = &MF.getRegInfo();  in canRealignStack()
400   const ARMFrameLowering *TFI = getFrameLowering(MF);  in canRealignStack()
404   if (!TargetRegisterInfo::canRealignStack(MF))  in canRealignStack()
408   if (!MRI->canReserveReg(getFramePointerReg(MF.getSubtarget<ARMSubtarget>())))  in canRealignStack()
412   if (TFI->hasReservedCallFrame(MF))  in canRealignStack()
420 cannotEliminateFrame(const MachineFunction &MF) const {  in cannotEliminateFrame()
421   const MachineFrameInfo &MFI = MF.getFrameInfo();  in cannotEliminateFrame()
422   if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI.adjustsStack())  in cannotEliminateFrame()
425     || needsStackRealignment(MF);  in cannotEliminateFrame()
429 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {  in getFrameRegister()
430   const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();  in getFrameRegister()
431   const ARMFrameLowering *TFI = getFrameLowering(MF);  in getFrameRegister()
433   if (TFI->hasFP(MF))  in getFrameRegister()
444   MachineFunction &MF = *MBB.getParent();  in emitLoadConstPool()  local
445   const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();  in emitLoadConstPool()
446   MachineConstantPool *ConstantPool = MF.getConstantPool();  in emitLoadConstPool()
448         ConstantInt::get(Type::getInt32Ty(MF.getFunction().getContext()), Val);  in emitLoadConstPool()
460 requiresRegisterScavenging(const MachineFunction &MF) const {  in requiresRegisterScavenging()
465 trackLivenessAfterRegAlloc(const MachineFunction &MF) const {  in trackLivenessAfterRegAlloc()
470 requiresFrameIndexScavenging(const MachineFunction &MF) const {  in requiresFrameIndexScavenging()
475 requiresVirtualBaseRegisters(const MachineFunction &MF) const {  in requiresVirtualBaseRegisters()
564   MachineFunction &MF = *MI->getParent()->getParent();  in needsFrameBaseReg()  local
565   const ARMFrameLowering *TFI = getFrameLowering(MF);  in needsFrameBaseReg()
566   MachineFrameInfo &MFI = MF.getFrameInfo();  in needsFrameBaseReg()
567   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();  in needsFrameBaseReg()
592   if (TFI->hasFP(MF) &&  in needsFrameBaseReg()
593       !((MFI.getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {  in needsFrameBaseReg()
594     if (isFrameOffsetLegal(MI, getFrameRegister(MF), FPOffset))  in needsFrameBaseReg()
624   const MachineFunction &MF = *MBB->getParent();  in materializeFrameBaseRegister()  local
626   const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();  in materializeFrameBaseRegister()
628   MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));  in materializeFrameBaseRegister()
640   MachineFunction &MF = *MBB.getParent();  in resolveFrameIndex()  local
642       *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());  in resolveFrameIndex()
643   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();  in resolveFrameIndex()
736   MachineFunction &MF = *MBB.getParent();  in eliminateFrameIndex()  local
738       *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());  in eliminateFrameIndex()
739   const ARMFrameLowering *TFI = getFrameLowering(MF);  in eliminateFrameIndex()
740   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();  in eliminateFrameIndex()
746   int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);  in eliminateFrameIndex()
754     assert(TFI->hasReservedCallFrame(MF) &&  in eliminateFrameIndex()
757     assert(!MF.getFrameInfo().hasVarSizedObjects() &&  in eliminateFrameIndex()
793     ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);  in eliminateFrameIndex()
815   auto MF = MBB->getParent();  in shouldCoalesce()  local
816   const MachineRegisterInfo &MRI = MF->getRegInfo();  in shouldCoalesce()
843   auto AFI = MF->getInfo<ARMFunctionInfo>();  in shouldCoalesce()