Lines Matching refs:DefAlign
3542 unsigned DefIdx, unsigned DefAlign) const { in getVLDMDefCycle()
3569 if ((isSLoad && (RegNo % 2)) || DefAlign < 8) in getVLDMDefCycle()
3599 unsigned DefIdx, unsigned DefAlign) const { in getLDMDefCycle()
3618 if ((RegNo % 2) || DefAlign < 8) in getLDMDefCycle()
3702 unsigned DefIdx, unsigned DefAlign, in getOperandLatency() argument
3727 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); in getOperandLatency()
3748 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); in getOperandLatency()
3868 const MCInstrDesc &DefMCID, unsigned DefAlign) { in adjustDefLatency() argument
3928 if (DefAlign < 8 && Subtarget.checkVLDnAccessAlignment()) { in adjustDefLatency()
4114 unsigned DefAlign = DefMI.hasOneMemOperand() in getOperandLatencyImpl() local
4122 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, UseMCID, in getOperandLatencyImpl()
4132 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign); in getOperandLatencyImpl()
4164 unsigned DefAlign = !DefMN->memoperands_empty() in getOperandLatency() local
4169 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, in getOperandLatency()
4229 if (DefAlign < 8 && Subtarget.checkVLDnAccessAlignment()) in getOperandLatency()
4458 unsigned DefAlign = in getInstrLatency() local
4460 int Adj = adjustDefLatency(Subtarget, MI, MCID, DefAlign); in getInstrLatency()