Lines Matching refs:CurReg
2334 unsigned CurReg = RegClass->getRegister(CurRegEnc); in tryFoldSPUpdateIntoPushPop() local
2339 RegList.push_back(MachineOperand::CreateReg(CurReg, false, false, in tryFoldSPUpdateIntoPushPop()
2349 if (isCalleeSavedRegister(CurReg, CSRegs) || in tryFoldSPUpdateIntoPushPop()
2350 MI->getParent()->computeRegisterLiveness(TRI, CurReg, MI) != in tryFoldSPUpdateIntoPushPop()
2361 RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false, in tryFoldSPUpdateIntoPushPop()
4845 unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst; in setExecutionDomain() local
4846 bool CurUndef = !MI.readsRegister(CurReg, TRI); in setExecutionDomain()
4847 NewMIB.addReg(CurReg, getUndefRegState(CurUndef)); in setExecutionDomain()
4849 CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst; in setExecutionDomain()
4850 CurUndef = !MI.readsRegister(CurReg, TRI); in setExecutionDomain()
4851 NewMIB.addReg(CurReg, getUndefRegState(CurUndef)) in setExecutionDomain()
4863 CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst; in setExecutionDomain()
4864 CurUndef = CurReg == DSrc && !MI.readsRegister(CurReg, TRI); in setExecutionDomain()
4865 MIB.addReg(CurReg, getUndefRegState(CurUndef)); in setExecutionDomain()
4867 CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst; in setExecutionDomain()
4868 CurUndef = CurReg == DSrc && !MI.readsRegister(CurReg, TRI); in setExecutionDomain()
4869 MIB.addReg(CurReg, getUndefRegState(CurUndef)) in setExecutionDomain()