110 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)  in ARMBaseInstrInfo()  function in ARMBaseInstrInfo
124 ARMBaseInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,  in CreateTargetHazardRecognizer()
134 ScheduleHazardRecognizer *ARMBaseInstrInfo::
142 MachineInstr *ARMBaseInstrInfo::convertToThreeAddress(  in convertToThreeAddress()
312 bool ARMBaseInstrInfo::analyzeBranch(MachineBasicBlock &MBB,  in analyzeBranch()
402 unsigned ARMBaseInstrInfo::removeBranch(MachineBasicBlock &MBB,  in removeBranch()
429 unsigned ARMBaseInstrInfo::insertBranch(MachineBasicBlock &MBB,  in insertBranch()
476 bool ARMBaseInstrInfo::
483 bool ARMBaseInstrInfo::isPredicated(const MachineInstr &MI) const {  in isPredicated()
499 bool ARMBaseInstrInfo::PredicateInstruction(  in PredicateInstruction()
520 bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,  in SubsumesPredicate()
546 bool ARMBaseInstrInfo::DefinesPredicate(  in DefinesPredicate()
561 bool ARMBaseInstrInfo::isCPSRDefined(const MachineInstr &MI) {  in isCPSRDefined()
568 bool ARMBaseInstrInfo::isAddrMode3OpImm(const MachineInstr &MI,  in isAddrMode3OpImm()
576 bool ARMBaseInstrInfo::isAddrMode3OpMinusReg(const MachineInstr &MI,  in isAddrMode3OpMinusReg()
588 bool ARMBaseInstrInfo::isLdstScaledReg(const MachineInstr &MI,  in isLdstScaledReg()
596 bool ARMBaseInstrInfo::isLdstScaledRegNotPlusLsl2(const MachineInstr &MI,  in isLdstScaledRegNotPlusLsl2()
610 bool ARMBaseInstrInfo::isLdstSoMinusReg(const MachineInstr &MI,  in isLdstSoMinusReg()
617 bool ARMBaseInstrInfo::isAm2ScaledReg(const MachineInstr &MI,  in isAm2ScaledReg()
648     return !ARMBaseInstrInfo::isCPSRDefined(*MI);  in isEligibleForITBlock()
655 bool ARMBaseInstrInfo::isPredicable(const MachineInstr &MI) const {  in isPredicable()
701 unsigned ARMBaseInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {  in getInstSizeInBytes()
758 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr &MI) const {  in getInstBundleLength()
769 void ARMBaseInstrInfo::copyFromCPSR(MachineBasicBlock &MBB,  in copyFromCPSR()
789 void ARMBaseInstrInfo::copyToCPSR(MachineBasicBlock &MBB,  in copyToCPSR()
809 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,  in copyPhysReg()
942 bool ARMBaseInstrInfo::isCopyInstrImpl(const MachineInstr &MI,  in isCopyInstrImpl()
962 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,  in AddDReg()
973 void ARMBaseInstrInfo::
1134 unsigned ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr &MI,  in isStoreToStackSlot()
1177 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,  in isStoreToStackSlotPostFE()
1189 void ARMBaseInstrInfo::
1348 unsigned ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,  in isLoadFromStackSlot()
1397 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,  in isLoadFromStackSlotPostFE()
1411 void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const {  in expandMEMCPY()
1414   const ARMBaseInstrInfo *TII = Subtarget.getInstrInfo();  in expandMEMCPY()
1465 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {  in expandPostRAPseudo()
1590 void ARMBaseInstrInfo::reMaterialize(MachineBasicBlock &MBB,  in reMaterialize()
1618 ARMBaseInstrInfo::duplicate(MachineBasicBlock &MBB,  in duplicate()
1642 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr &MI0,  in produceSameValue()
1737 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,  in areLoadsFromSameBasePtr()
1818 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,  in shouldScheduleLoadsNear()
1848 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr &MI,  in isSchedulingBoundary()
1891 bool ARMBaseInstrInfo::
1926 bool ARMBaseInstrInfo::
1982 ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,  in isProfitableToUnpredicate()
2015 MachineInstr *ARMBaseInstrInfo::commuteInstructionImpl(MachineInstr &MI,  in commuteInstructionImpl()
2079 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr &MI,  in analyzeSelect()
2101 ARMBaseInstrInfo::optimizeSelect(MachineInstr &MI,  in optimizeSelect()
2228                                    const ARMBaseInstrInfo &TII,  in emitARMRegPlusImmediate()
2385                                 const ARMBaseInstrInfo &TII) {  in rewriteARMFrameIndex()
2531 bool ARMBaseInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,  in analyzeCompare()
2715 bool ARMBaseInstrInfo::optimizeCompareInstr(  in optimizeCompareInstr()
2980 bool ARMBaseInstrInfo::shouldSink(const MachineInstr &MI) const {  in shouldSink()
2997 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,  in FoldImmediate()
3376 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr &MI) const {  in getNumLDMAddresses()
3425 unsigned ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,  in getNumMicroOps()
3539 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,  in getVLDMDefCycle()
3579 bool ARMBaseInstrInfo::isLDMBaseRegInList(const MachineInstr &MI) const {  in isLDMBaseRegInList()
3589 ARMBaseInstrInfo::getLDMVariableDefsSize(const MachineInstr &MI) const {  in getLDMVariableDefsSize()
3596 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,  in getLDMDefCycle()
3631 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,  in getVSTMUseCycle()
3671 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,  in getSTMUseCycle()
3700 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,  in getOperandLatency()
4044 int ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,  in getOperandLatency()
4080 int ARMBaseInstrInfo::getOperandLatencyImpl(  in getOperandLatencyImpl()
4141 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,  in getOperandLatency()
4397 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr &MI) const {  in getPredicationCost()
4416 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,  in getInstrLatency()
4467 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,  in getInstrLatency()
4485 bool ARMBaseInstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,  in hasHighOperandLatency()
4506 bool ARMBaseInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,  in hasLowDefLatency()
4522 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr &MI,  in verifyInstruction()
4533 void ARMBaseInstrInfo::expandLoadStackGuardBase(MachineBasicBlock::iterator MI,  in expandLoadStackGuardBase()
4568 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,  in isFpMLxInstruction()
4604 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr &MI) const {  in getExecutionDomain()
4694 void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI,  in setExecutionDomain()
4902 unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance(  in getPartialRegUpdateClearance()
4963 void ARMBaseInstrInfo::breakPartialRegDependency(  in breakPartialRegDependency()
4997 bool ARMBaseInstrInfo::hasNOP() const {  in hasNOP()
5001 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {  in isSwiftFastImmShift()
5015 bool ARMBaseInstrInfo::getRegSequenceLikeInputs(  in getRegSequenceLikeInputs()
5042 bool ARMBaseInstrInfo::getExtractSubregLikeInputs(  in getExtractSubregLikeInputs()
5065 bool ARMBaseInstrInfo::getInsertSubregLikeInputs(  in getInsertSubregLikeInputs()
5091 ARMBaseInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {  in decomposeMachineOperandsTargetFlags()
5097 ARMBaseInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {  in getSerializableDirectMachineOperandTargetFlags()
5106 ARMBaseInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {  in getSerializableBitmaskMachineOperandTargetFlags()