453         BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).add(predOps(ARMCC::AL));  in insertBranch()
470     BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).add(predOps(ARMCC::AL));  in insertBranch()
489       if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)  in isPredicated()
496   return PIdx != -1 && MI.getOperand(PIdx).getImm() != ARMCC::AL;  in isPredicated()
533   case ARMCC::AL:  in SubsumesPredicate()
785   MIB.add(predOps(ARMCC::AL))  in copyFromCPSR()
805      .add(predOps(ARMCC::AL))  in copyToCPSR()
819         .add(predOps(ARMCC::AL))  in copyPhysReg()
844     MIB.add(predOps(ARMCC::AL));  in copyPhysReg()
931     Mov = Mov.add(predOps(ARMCC::AL));  in copyPhysReg()
994             .add(predOps(ARMCC::AL));  in storeRegToStackSlot()
1005             .add(predOps(ARMCC::AL));  in storeRegToStackSlot()
1012             .add(predOps(ARMCC::AL));  in storeRegToStackSlot()
1023             .add(predOps(ARMCC::AL));  in storeRegToStackSlot()
1030              .add(predOps(ARMCC::AL));  in storeRegToStackSlot()
1037                                         .add(predOps(ARMCC::AL));  in storeRegToStackSlot()
1053               .add(predOps(ARMCC::AL));  in storeRegToStackSlot()
1059               .add(predOps(ARMCC::AL));  in storeRegToStackSlot()
1073               .add(predOps(ARMCC::AL));  in storeRegToStackSlot()
1078                                         .add(predOps(ARMCC::AL))  in storeRegToStackSlot()
1097               .add(predOps(ARMCC::AL));  in storeRegToStackSlot()
1102                                         .add(predOps(ARMCC::AL))  in storeRegToStackSlot()
1116                                       .add(predOps(ARMCC::AL))  in storeRegToStackSlot()
1210           .add(predOps(ARMCC::AL));  in loadRegFromStackSlot()
1220           .add(predOps(ARMCC::AL));  in loadRegFromStackSlot()
1226           .add(predOps(ARMCC::AL));  in loadRegFromStackSlot()
1236           .add(predOps(ARMCC::AL));  in loadRegFromStackSlot()
1245            .add(predOps(ARMCC::AL));  in loadRegFromStackSlot()
1252                   .add(predOps(ARMCC::AL));  in loadRegFromStackSlot()
1269             .add(predOps(ARMCC::AL));  in loadRegFromStackSlot()
1274             .add(predOps(ARMCC::AL));  in loadRegFromStackSlot()
1286             .add(predOps(ARMCC::AL));  in loadRegFromStackSlot()
1291                                       .add(predOps(ARMCC::AL));  in loadRegFromStackSlot()
1308             .add(predOps(ARMCC::AL));  in loadRegFromStackSlot()
1312                                       .add(predOps(ARMCC::AL))  in loadRegFromStackSlot()
1328                                     .add(predOps(ARMCC::AL))  in loadRegFromStackSlot()
1441   LDM.add(LDBase).add(predOps(ARMCC::AL));  in expandMEMCPY()
1444   STM.add(STBase).add(predOps(ARMCC::AL));  in expandMEMCPY()
1525   MIB.add(predOps(ARMCC::AL));  in expandPostRAPseudo()
1914             if (P == ARMCC::AL && CmpMI->getOperand(1).getImm() == 0 &&  in isProfitableToIfCvt()
1997     return ARMCC::AL;  in getInstrPredicate()
2026     if (CC == ARMCC::AL || PredReg != ARM::CPSR)  in commuteInstructionImpl()
2587   default: return ARMCC::AL;  in getSwappedCondition()
2606   default: return ARMCC::AL;  in getCmpToAddCondition()
2918           if (NewCC == ARMCC::AL)  in optimizeCompareInstr()
2930         case ARMCC::AL: // none  in optimizeCompareInstr()
3118       .add(predOps(ARMCC::AL))  in FoldImmediate()
4557     MIB.addMemOperand(MMO).add(predOps(ARMCC::AL));  in expandLoadStackGuardBase()
4564       .add(predOps(ARMCC::AL));  in expandLoadStackGuardBase()
4726         .add(predOps(ARMCC::AL));  in setExecutionDomain()
4749         .add(predOps(ARMCC::AL));  in setExecutionDomain()
4780         .add(predOps(ARMCC::AL));  in setExecutionDomain()
4815             .add(predOps(ARMCC::AL));  in setExecutionDomain()
4853             .add(predOps(ARMCC::AL));  in setExecutionDomain()
4871          .add(predOps(ARMCC::AL));  in setExecutionDomain()
4993       .add(predOps(ARMCC::AL));  in breakPartialRegDependency()