422   unsigned Out = MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass :  in createDupLane()  local
425           TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d), Out)  in createDupLane()
430   return Out;  in createDupLane()
438   unsigned Out = MRI->createVirtualRegister(TRC);  in createExtractSubreg()  local
442           TII->get(TargetOpcode::COPY), Out)  in createExtractSubreg()
445   return Out;  in createExtractSubreg()
452   unsigned Out = MRI->createVirtualRegister(&ARM::QPRRegClass);  in createRegSequence()  local
456           TII->get(TargetOpcode::REG_SEQUENCE), Out)  in createRegSequence()
461   return Out;  in createRegSequence()
470   unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);  in createVExt()  local
471   BuildMI(MBB, InsertBefore, DL, TII->get(ARM::VEXTd32), Out)  in createVExt()
476   return Out;  in createVExt()
482   unsigned Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass);  in createInsertSubreg()  local
486           TII->get(TargetOpcode::INSERT_SUBREG), Out)  in createInsertSubreg()
491   return Out;  in createInsertSubreg()
498   unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);  in createImplicitDef()  local
502           TII->get(TargetOpcode::IMPLICIT_DEF), Out);  in createImplicitDef()
503   return Out;  in createImplicitDef()
515   unsigned Out;  in optimizeAllLanesPattern()  local
528     Out = createVExt(MBB, InsertPt, DL, Out1, Out2);  in optimizeAllLanesPattern()
534     Out = createRegSequence(MBB, InsertPt, DL, Out, Out2);  in optimizeAllLanesPattern()
539     Out = createVExt(MBB, InsertPt, DL, Out1, Out2);  in optimizeAllLanesPattern()
557     Out = createImplicitDef(MBB, InsertPt, DL);  in optimizeAllLanesPattern()
558     Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg);  in optimizeAllLanesPattern()
559     Out = createDupLane(MBB, InsertPt, DL, Out, Lane, UsesQPR);  in optimizeAllLanesPattern()
562   return Out;  in optimizeAllLanesPattern()