Lines Matching refs:DebugLoc
69 const DebugLoc &DL, unsigned Reg, unsigned Lane,
74 const DebugLoc &DL, unsigned DReg,
79 const DebugLoc &DL, unsigned Ssub0, unsigned Ssub1);
83 const DebugLoc &DL, unsigned Reg1,
88 const DebugLoc &DL, unsigned DReg,
93 const DebugLoc &DL);
420 const DebugLoc &DL, unsigned Reg, in createDupLane()
436 const DebugLoc &DL, unsigned DReg, unsigned Lane, in createExtractSubreg()
451 const DebugLoc &DL, unsigned Reg1, unsigned Reg2) { in createRegSequence()
468 const DebugLoc &DL, unsigned Ssub0, in createVExt()
481 const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) { in createInsertSubreg()
497 const DebugLoc &DL) { in createImplicitDef()
512 DebugLoc DL = MI->getDebugLoc(); in optimizeAllLanesPattern()