Lines Matching refs:ARC
35 : ARCGenInstrInfo(ARC::ADJCALLSTACKDOWN, ARC::ADJCALLSTACKUP), RI() {} in ARCInstrInfo()
42 return Opcode == ARC::LD_rs9 || Opcode == ARC::LDH_rs9 || in isLoad()
43 Opcode == ARC::LDB_rs9; in isLoad()
47 return Opcode == ARC::ST_rs9 || Opcode == ARC::STH_rs9 || in isStore()
48 Opcode == ARC::STB_rs9; in isStore()
125 static bool isUncondBranchOpcode(int Opc) { return Opc == ARC::BR; } in isUncondBranchOpcode()
128 return Opc == ARC::BRcc_rr_p || Opc == ARC::BRcc_ru6_p; in isCondBranchOpcode()
131 static bool isJumpOpcode(int Opc) { return Opc == ARC::J; } in isJumpOpcode()
273 assert(ARC::GPR32RegClass.contains(SrcReg) && in copyPhysReg()
275 assert(ARC::GPR32RegClass.contains(DestReg) && in copyPhysReg()
277 BuildMI(MBB, I, dl, get(ARC::MOV_rr), DestReg) in copyPhysReg()
299 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in storeRegToStackSlot()
303 BuildMI(MBB, I, dl, get(ARC::ST_rs9)) in storeRegToStackSlot()
326 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in loadRegFromStackSlot()
330 BuildMI(MBB, I, dl, get(ARC::LD_rs9)) in loadRegFromStackSlot()
351 return BuildMI(MBB, MI, dl, get(ARC::MOV_rs12), Reg) in loadImmediate()
371 BuildMI(&MBB, dl, get(ARC::BR)).addMBB(TBB); in insertBranch()
374 int BccOpc = Cond[1].isImm() ? ARC::BRcc_ru6_p : ARC::BRcc_rr_p; in insertBranch()
387 BuildMI(&MBB, dl, get(ARC::BR)).addMBB(FBB); in insertBranch()