45 static unsigned insertUndefLaneMask(MachineBasicBlock &MBB);
84   void buildMergeLaneMasks(MachineBasicBlock &MBB,
88   getSaluInsertionAtEnd(MachineBasicBlock &MBB) const;
134   bool isSource(MachineBasicBlock &MBB) const {  in isSource()
135     return ReachableMap.find(&MBB)->second;  in isSource()
152     for (MachineBasicBlock *MBB : IncomingBlocks) {  in analyze()
153       if (MBB == &DefBlock) {  in analyze()
158       ReachableMap.try_emplace(MBB, false);  in analyze()
159       ReachableOrdered.push_back(MBB);  in analyze()
164       for (MachineInstr &MI : MBB->terminators()) {  in analyze()
174       if (Divergent && PDT.dominates(&DefBlock, MBB)) {  in analyze()
175         for (MachineBasicBlock *Succ : MBB->successors())  in analyze()
181       MachineBasicBlock *MBB = Stack.pop_back_val();  in analyze()  local
182       if (!ReachableMap.try_emplace(MBB, false).second)  in analyze()
184       ReachableOrdered.push_back(MBB);  in analyze()
186       for (MachineBasicBlock *Succ : MBB->successors())  in analyze()
190     for (MachineBasicBlock *MBB : ReachableOrdered) {  in analyze()
192       for (MachineBasicBlock *Pred : MBB->predecessors()) {  in analyze()
200         ReachableMap[MBB] = true;  in analyze()
273   void initialize(MachineBasicBlock &MBB) {  in initialize()  argument
281     DefBlock = &MBB;  in initialize()
315     for (MachineBasicBlock *MBB : Blocks)
316       Dom = DT.findNearestCommonDominator(Dom, MBB);
331   bool inLoopLevel(MachineBasicBlock &MBB, unsigned LoopLevel,  in inLoopLevel()  argument
333     auto DomIt = Visited.find(&MBB);  in inLoopLevel()
337     if (llvm::find(Blocks, &MBB) != Blocks.end())  in inLoopLevel()
368       MachineBasicBlock *MBB = Stack.pop_back_val();  in advanceLevel()  local
369       if (!PDT.dominates(VisitedPostDom, MBB))  in advanceLevel()
370         NextLevel.push_back(MBB);  in advanceLevel()
372       Visited[MBB] = Level;  in advanceLevel()
373       VisitedDom = DT.findNearestCommonDominator(VisitedDom, MBB);  in advanceLevel()
375       for (MachineBasicBlock *Succ : MBB->successors()) {  in advanceLevel()
377           if (MBB == VisitedPostDom)  in advanceLevel()
385           if (MBB == VisitedPostDom)  in advanceLevel()
419 static unsigned insertUndefLaneMask(MachineBasicBlock &MBB) {  in insertUndefLaneMask()  argument
420   MachineFunction &MF = *MBB.getParent();  in insertUndefLaneMask()
424   BuildMI(MBB, MBB.getFirstTerminator(), {}, TII->get(AMDGPU::IMPLICIT_DEF),  in insertUndefLaneMask()
461   for (MachineBasicBlock &MBB : *MF) {  in lowerCopiesFromI1()
462     for (MachineInstr &MI : MBB) {  in lowerCopiesFromI1()
485       BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstReg)  in lowerCopiesFromI1()
507   for (MachineBasicBlock &MBB : *MF) {  in lowerPhis()
508     LF.initialize(MBB);  in lowerPhis()
510     for (MachineInstr &MI : MBB.phis()) {  in lowerPhis()
542       MachineBasicBlock *PostDomBound = &MBB;  in lowerPhis()
570         PIA.analyze(MBB, IncomingBlocks);  in lowerPhis()
572         for (MachineBasicBlock *MBB : PIA.predecessors())  in lowerPhis()
573           SSAUpdater.AddAvailableValue(MBB, insertUndefLaneMask(*MBB));  in lowerPhis()
597       unsigned NewReg = SSAUpdater.GetValueInMiddleOfBlock(&MBB);  in lowerPhis()
623   for (MachineBasicBlock &MBB : *MF) {  in lowerCopiesToI1()
624     LF.initialize(MBB);  in lowerCopiesToI1()
626     for (MachineInstr &MI : MBB) {  in lowerCopiesToI1()
655         BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CMP_NE_U32_e64), TmpReg)  in lowerCopiesToI1()
664       MachineBasicBlock *PostDomBound = &MBB;  in lowerCopiesToI1()
673         SSAUpdater.AddAvailableValue(&MBB, DstReg);  in lowerCopiesToI1()
676         buildMergeLaneMasks(MBB, MI, DL, DstReg,  in lowerCopiesToI1()
677                             SSAUpdater.GetValueInMiddleOfBlock(&MBB), SrcReg);  in lowerCopiesToI1()
738 SILowerI1Copies::getSaluInsertionAtEnd(MachineBasicBlock &MBB) const {  in getSaluInsertionAtEnd()
739   auto InsertionPt = MBB.getFirstTerminator();  in getSaluInsertionAtEnd()
741   for (auto I = InsertionPt, E = MBB.end(); I != E; ++I) {  in getSaluInsertionAtEnd()
751   while (InsertionPt != MBB.begin()) {  in getSaluInsertionAtEnd()
764 void SILowerI1Copies::buildMergeLaneMasks(MachineBasicBlock &MBB,  in buildMergeLaneMasks()  argument
775       BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(CurReg);  in buildMergeLaneMasks()
777       BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(AMDGPU::EXEC);  in buildMergeLaneMasks()
779       BuildMI(MBB, I, DL, TII->get(AMDGPU::S_XOR_B64), DstReg)  in buildMergeLaneMasks()
793       BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ANDN2_B64), PrevMaskedReg)  in buildMergeLaneMasks()
804       BuildMI(MBB, I, DL, TII->get(AMDGPU::S_AND_B64), CurMaskedReg)  in buildMergeLaneMasks()
811     BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg)  in buildMergeLaneMasks()
814     BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg)  in buildMergeLaneMasks()
817     BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ORN2_B64), DstReg)  in buildMergeLaneMasks()
821     BuildMI(MBB, I, DL, TII->get(AMDGPU::S_OR_B64), DstReg)  in buildMergeLaneMasks()