155   const GCNSubtarget *STM = nullptr;  member in __anon16dce4e40111::SILoadStoreOptimizer
163   static bool widthsFit(const GCNSubtarget &STM, const CombineInfo &CI);
370 bool SILoadStoreOptimizer::widthsFit(const GCNSubtarget &STM,  in widthsFit()  argument
375     return (Width <= 4) && (STM.hasDwordx3LoadStores() || (Width != 3));  in widthsFit()
649       if (widthsFit(*STM, CI) && offsetsCanBeCombined(CI))  in findMatchingInst()
667   if (STM->ldsRequiresM0Init())  in read2Opcode()
673   if (STM->ldsRequiresM0Init())  in read2ST64Opcode()
764   if (STM->ldsRequiresM0Init())  in write2Opcode()
771   if (STM->ldsRequiresM0Init())  in write2ST64Opcode()
1340     static_cast<const SITargetLowering *>(STM->getTargetLowering());  in promoteConstantOffsetToImm()
1467       CI.EltSize = AMDGPU::getSMRDEncodedOffset(*STM, 4);  in optimizeBlock()
1514   STM = &MF.getSubtarget<GCNSubtarget>();  in runOnMachineFunction()
1515   if (!STM->loadStoreOptEnabled())  in runOnMachineFunction()
1518   TII = STM->getInstrInfo();  in runOnMachineFunction()