88 SIInstrInfo::SIInstrInfo(const GCNSubtarget &ST)  in SIInstrInfo()  function in SIInstrInfo
136 bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,  in isReallyTriviallyReMaterializable()
151 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,  in areLoadsFromSameBasePtr()
268 bool SIInstrInfo::getMemOperandWithOffset(MachineInstr &LdSt,  in getMemOperandWithOffset()
416 bool SIInstrInfo::shouldClusterMemOps(MachineOperand &BaseOp1,  in shouldClusterMemOps()
479 bool SIInstrInfo::shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1,  in shouldScheduleLoadsNear()
491 static void reportIllegalCopy(const SIInstrInfo *TII, MachineBasicBlock &MBB,  in reportIllegalCopy()
506 void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,  in copyPhysReg()
613 int SIInstrInfo::commuteOpcode(unsigned Opcode) const {  in commuteOpcode()
631 void SIInstrInfo::materializeImmediate(MachineBasicBlock &MBB,  in materializeImmediate()
688 SIInstrInfo::getPreferredSelectRegClass(unsigned Size) const {  in getPreferredSelectRegClass()
692 void SIInstrInfo::insertVectorSelect(MachineBasicBlock &MBB,  in insertVectorSelect()
713     case SIInstrInfo::SCC_TRUE: {  in insertVectorSelect()
724     case SIInstrInfo::SCC_FALSE: {  in insertVectorSelect()
735     case SIInstrInfo::VCCNZ: {  in insertVectorSelect()
747     case SIInstrInfo::VCCZ: {  in insertVectorSelect()
759     case SIInstrInfo::EXECNZ: {  in insertVectorSelect()
773     case SIInstrInfo::EXECZ: {  in insertVectorSelect()
796 unsigned SIInstrInfo::insertEQ(MachineBasicBlock *MBB,  in insertEQ()
809 unsigned SIInstrInfo::insertNE(MachineBasicBlock *MBB,  in insertNE()
822 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {  in getMovOpcode()
870 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,  in storeRegToStackSlot()
972 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,  in loadRegFromStackSlot()
1029 unsigned SIInstrInfo::calculateLDSSpillAddress(  in calculateLDSSpillAddress()
1122 void SIInstrInfo::insertWaitStates(MachineBasicBlock &MBB,  in insertWaitStates()
1138 void SIInstrInfo::insertNoop(MachineBasicBlock &MBB,  in insertNoop()
1143 void SIInstrInfo::insertReturn(MachineBasicBlock &MBB) const {  in insertReturn()
1157 unsigned SIInstrInfo::getNumWaitStates(const MachineInstr &MI) const {  in getNumWaitStates()
1166 bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {  in expandPostRAPseudo()
1285     if (MI.getOperand(2).getTargetFlags() == SIInstrInfo::MO_NONE)  in expandPostRAPseudo()
1322 bool SIInstrInfo::swapSourceModifiers(MachineInstr &MI,  in swapSourceModifiers()
1366 MachineInstr *SIInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,  in commuteInstructionImpl()
1418 bool SIInstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx0,  in findCommutedOpIndices()
1423 bool SIInstrInfo::findCommutedOpIndices(MCInstrDesc Desc, unsigned &SrcOpIdx0,  in findCommutedOpIndices()
1440 bool SIInstrInfo::isBranchOffsetInRange(unsigned BranchOp,  in isBranchOffsetInRange()
1456 MachineBasicBlock *SIInstrInfo::getBranchDestBlock(  in getBranchDestBlock()
1467 unsigned SIInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,  in insertIndirectBranch()
1563 unsigned SIInstrInfo::getBranchOpcode(SIInstrInfo::BranchPredicate Cond) {  in getBranchOpcode()
1565   case SIInstrInfo::SCC_TRUE:  in getBranchOpcode()
1567   case SIInstrInfo::SCC_FALSE:  in getBranchOpcode()
1569   case SIInstrInfo::VCCNZ:  in getBranchOpcode()
1571   case SIInstrInfo::VCCZ:  in getBranchOpcode()
1573   case SIInstrInfo::EXECNZ:  in getBranchOpcode()
1575   case SIInstrInfo::EXECZ:  in getBranchOpcode()
1582 SIInstrInfo::BranchPredicate SIInstrInfo::getBranchPredicate(unsigned Opcode) {  in getBranchPredicate()
1601 bool SIInstrInfo::analyzeBranchImpl(MachineBasicBlock &MBB,  in analyzeBranchImpl()
1644 bool SIInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,  in analyzeBranch()
1709 unsigned SIInstrInfo::removeBranch(MachineBasicBlock &MBB,  in removeBranch()
1741 unsigned SIInstrInfo::insertBranch(MachineBasicBlock &MBB,  in insertBranch()
1799 bool SIInstrInfo::reverseBranchCondition(  in reverseBranchCondition()
1813 bool SIInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,  in canInsertSelect()
1853 void SIInstrInfo::insertSelect(MachineBasicBlock &MBB,  in insertSelect()
1943 bool SIInstrInfo::isFoldableCopy(const MachineInstr &MI) const {  in isFoldableCopy()
1964 unsigned SIInstrInfo::getAddressSpaceForPseudoSourceKind(  in getAddressSpaceForPseudoSourceKind()
1995 bool SIInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,  in FoldImmediate()
2175 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr &MIa,  in checkInstOffsetsDoNotOverlap()
2199 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr &MIa,  in areMemAccessesTriviallyDisjoint()
2273 MachineInstr *SIInstrInfo::convertToThreeAddress(MachineFunction::iterator &MBB,  in convertToThreeAddress()
2378 bool SIInstrInfo::isSchedulingBoundary(const MachineInstr &MI,  in isSchedulingBoundary()
2393 bool SIInstrInfo::isAlwaysGDS(uint16_t Opcode) const {  in isAlwaysGDS()
2403 bool SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const {  in hasUnwantedEffectsWhenEXECEmpty()
2434 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {  in isInlineConstant()
2451 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,  in isInlineConstant()
2513 bool SIInstrInfo::isLiteralConstantLike(const MachineOperand &MO,  in isLiteralConstantLike()
2546 bool SIInstrInfo::isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,  in isImmOperandLegal()
2564 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {  in hasVALU32BitEncoding()
2572 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {  in hasModifiers()
2580 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,  in hasModifiersSet()
2586 bool SIInstrInfo::hasAnyModifiersSet(const MachineInstr &MI) const {  in hasAnyModifiersSet()
2594 bool SIInstrInfo::canShrink(const MachineInstr &MI,  in canShrink()
2663 MachineInstr *SIInstrInfo::buildShrunkInst(MachineInstr &MI,  in buildShrunkInst()
2703 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,  in usesConstantBus()
2757   if (SIInstrInfo::isVALU(MI)) {  in shouldReadExec()
2771   if (SIInstrInfo::isGenericOpcode(MI.getOpcode()) ||  in shouldReadExec()
2772       SIInstrInfo::isSALU(MI) ||  in shouldReadExec()
2773       SIInstrInfo::isSMRD(MI))  in shouldReadExec()
2789 bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,  in verifyInstruction()
2792   if (SIInstrInfo::isGenericOpcode(MI.getOpcode()))  in verifyInstruction()
3188 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) const {  in getVALUOp()
3260 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,  in getOpRegClass()
3277 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {  in canReadVGPR()
3289 void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const {  in legalizeOpWithMove()
3314 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,  in buildExtractSubReg()
3346 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(  in buildExtractSubRegOrImm()
3368 void SIInstrInfo::swapOperands(MachineInstr &Inst) const {  in swapOperands()
3375 bool SIInstrInfo::isLegalRegOperand(const MachineRegisterInfo &MRI,  in isLegalRegOperand()
3403 bool SIInstrInfo::isLegalVSrcOperand(const MachineRegisterInfo &MRI,  in isLegalVSrcOperand()
3414 bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,  in isOperandLegal()
3461 void SIInstrInfo::legalizeOperandsVOP2(MachineRegisterInfo &MRI,  in legalizeOperandsVOP2()
3576 void SIInstrInfo::legalizeOperandsVOP3(MachineRegisterInfo &MRI,  in legalizeOperandsVOP3()
3614 unsigned SIInstrInfo::readlaneVGPRToSGPR(unsigned SrcReg, MachineInstr &UseMI,  in readlaneVGPRToSGPR()
3647 void SIInstrInfo::legalizeOperandsSMRD(MachineRegisterInfo &MRI,  in legalizeOperandsSMRD()
3666 void SIInstrInfo::legalizeGenericOperand(MachineBasicBlock &InsertMBB,  in legalizeGenericOperand()
3702 emitLoadSRsrcFromVGPRLoop(const SIInstrInfo &TII, MachineRegisterInfo &MRI,  in emitLoadSRsrcFromVGPRLoop()
3773 static void loadSRsrcFromVGPR(const SIInstrInfo &TII, MachineInstr &MI,  in loadSRsrcFromVGPR()
3840 extractRsrcPtr(const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc) {  in extractRsrcPtr()
3881 void SIInstrInfo::legalizeOperands(MachineInstr &MI,  in legalizeOperands()
4160 void SIInstrInfo::moveToVALU(MachineInstr &TopInst,  in moveToVALU()
4436 bool SIInstrInfo::moveScalarAddSub(SetVectorType &Worklist, MachineInstr &Inst,  in moveScalarAddSub()
4470 void SIInstrInfo::lowerScalarAbs(SetVectorType &Worklist,  in lowerScalarAbs()
4497 void SIInstrInfo::lowerScalarXnor(SetVectorType &Worklist,  in lowerScalarXnor()
4565 void SIInstrInfo::splitScalarNotBinop(SetVectorType &Worklist,  in splitScalarNotBinop()
4594 void SIInstrInfo::splitScalarBinOpN2(SetVectorType& Worklist,  in splitScalarBinOpN2()
4623 void SIInstrInfo::splitScalar64BitUnaryOp(  in splitScalar64BitUnaryOp()
4677 void SIInstrInfo::splitScalar64BitAddSub(SetVectorType &Worklist,  in splitScalar64BitAddSub()
4746 void SIInstrInfo::splitScalar64BitBinaryOp(SetVectorType &Worklist,  in splitScalar64BitBinaryOp()
4810 void SIInstrInfo::splitScalar64BitXnor(SetVectorType &Worklist,  in splitScalar64BitXnor()
4852 void SIInstrInfo::splitScalar64BitBCNT(  in splitScalar64BitBCNT()
4889 void SIInstrInfo::splitScalar64BitBFE(SetVectorType &Worklist,  in splitScalar64BitBFE()
4950 void SIInstrInfo::addUsersToMoveToVALUWorklist(  in addUsersToMoveToVALUWorklist()
4969 void SIInstrInfo::movePackToVALU(SetVectorType &Worklist,  in movePackToVALU()
5031 void SIInstrInfo::addSCCDefUsersToVALUWorklist(  in addSCCDefUsersToVALUWorklist()
5047 const TargetRegisterClass *SIInstrInfo::getDestEquivalentVGPRClass(  in getDestEquivalentVGPRClass()
5074 unsigned SIInstrInfo::findUsedSGPR(const MachineInstr &MI,  in findUsedSGPR()
5143 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,  in getNamedOperand()
5152 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {  in getDefaultRsrcDataFormat()
5168 uint64_t SIInstrInfo::getScratchRsrcWords23() const {  in getScratchRsrcWords23()
5190 bool SIInstrInfo::isLowLatencyInstruction(const MachineInstr &MI) const {  in isLowLatencyInstruction()
5196 bool SIInstrInfo::isHighLatencyInstruction(const MachineInstr &MI) const {  in isHighLatencyInstruction()
5202 unsigned SIInstrInfo::isStackAccess(const MachineInstr &MI,  in isStackAccess()
5215 unsigned SIInstrInfo::isSGPRStackAccess(const MachineInstr &MI,  in isSGPRStackAccess()
5223 unsigned SIInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,  in isLoadFromStackSlot()
5237 unsigned SIInstrInfo::isStoreToStackSlot(const MachineInstr &MI,  in isStoreToStackSlot()
5251 unsigned SIInstrInfo::getInstBundleSize(const MachineInstr &MI) const {  in getInstBundleSize()
5263 unsigned SIInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {  in getInstSizeInBytes()
5318 bool SIInstrInfo::mayAccessFlatAddressSpace(const MachineInstr &MI) const {  in mayAccessFlatAddressSpace()
5332 bool SIInstrInfo::isNonUniformBranchInstr(MachineInstr &Branch) const {  in isNonUniformBranchInstr()
5336 void SIInstrInfo::convertNonUniformIfRegion(MachineBasicBlock *IfEntry,  in convertNonUniformIfRegion()
5361 void SIInstrInfo::convertNonUniformLoopRegion(  in convertNonUniformLoopRegion()
5409 SIInstrInfo::getSerializableTargetIndices() const {  in getSerializableTargetIndices()
5422 SIInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,  in CreateTargetPostRAHazardRecognizer()
5430 SIInstrInfo::CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const {  in CreateTargetPostRAHazardRecognizer()
5435 SIInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {  in decomposeMachineOperandsTargetFlags()
5440 SIInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {  in getSerializableDirectMachineOperandTargetFlags()
5452 bool SIInstrInfo::isBasicBlockPrologue(const MachineInstr &MI) const {  in isBasicBlockPrologue()
5458 SIInstrInfo::getAddNoCarry(MachineBasicBlock &MBB,  in getAddNoCarry()
5473 bool SIInstrInfo::isKillTerminator(unsigned Opcode) {  in isKillTerminator()
5483 const MCInstrDesc &SIInstrInfo::getKillTerminatorFromPseudo(unsigned Opcode) const {  in getKillTerminatorFromPseudo()
5494 bool SIInstrInfo::isBufferSMRD(const MachineInstr &MI) const {  in isBufferSMRD()
5531 int SIInstrInfo::pseudoToMCOpcode(int Opcode) const {  in pseudoToMCOpcode()