Lines Matching refs:Rsrc
3704 const DebugLoc &DL, MachineOperand &Rsrc) { in emitLoadSRsrcFromVGPRLoop() argument
3707 unsigned VRsrc = Rsrc.getReg(); in emitLoadSRsrcFromVGPRLoop()
3708 unsigned VRsrcUndef = getUndefRegState(Rsrc.isUndef()); in emitLoadSRsrcFromVGPRLoop()
3741 Rsrc.setReg(SRsrc); in emitLoadSRsrcFromVGPRLoop()
3742 Rsrc.setIsKill(true); in emitLoadSRsrcFromVGPRLoop()
3774 MachineOperand &Rsrc, MachineDominatorTree *MDT) { in loadSRsrcFromVGPR() argument
3830 emitLoadSRsrcFromVGPRLoop(TII, MRI, MBB, *LoopBB, DL, Rsrc); in loadSRsrcFromVGPR()
3840 extractRsrcPtr(const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc) { in extractRsrcPtr() argument
3847 TII.buildExtractSubReg(MI, MRI, Rsrc, &AMDGPU::VReg_128RegClass, in extractRsrcPtr()
4029 MachineOperand *Rsrc = &MI.getOperand(RsrcIdx); in legalizeOperands() local
4031 if (RI.getCommonSubClass(MRI.getRegClass(Rsrc->getReg()), in legalizeOperands()
4062 std::tie(RsrcPtr, NewSRsrc) = extractRsrcPtr(*this, MI, *Rsrc); in legalizeOperands()
4083 Rsrc->setReg(NewSRsrc); in legalizeOperands()
4092 std::tie(RsrcPtr, NewSRsrc) = extractRsrcPtr(*this, MI, *Rsrc); in legalizeOperands()
4155 loadSRsrcFromVGPR(*this, MI, *Rsrc, MDT); in legalizeOperands()