Lines Matching refs:LoopBB
3703 MachineBasicBlock &OrigBB, MachineBasicBlock &LoopBB, in emitLoadSRsrcFromVGPRLoop() argument
3705 MachineBasicBlock::iterator I = LoopBB.begin(); in emitLoadSRsrcFromVGPRLoop()
3721 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub0) in emitLoadSRsrcFromVGPRLoop()
3723 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub1) in emitLoadSRsrcFromVGPRLoop()
3725 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub2) in emitLoadSRsrcFromVGPRLoop()
3727 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub3) in emitLoadSRsrcFromVGPRLoop()
3730 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), SRsrc) in emitLoadSRsrcFromVGPRLoop()
3745 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_CMP_EQ_U64_e64), CondReg0) in emitLoadSRsrcFromVGPRLoop()
3748 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_CMP_EQ_U64_e64), CondReg1) in emitLoadSRsrcFromVGPRLoop()
3751 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::S_AND_B64), AndCond) in emitLoadSRsrcFromVGPRLoop()
3758 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::S_AND_SAVEEXEC_B64), SaveExec) in emitLoadSRsrcFromVGPRLoop()
3762 I = LoopBB.end(); in emitLoadSRsrcFromVGPRLoop()
3765 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::S_XOR_B64_term), AMDGPU::EXEC) in emitLoadSRsrcFromVGPRLoop()
3768 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::S_CBRANCH_EXECNZ)).addMBB(&LoopBB); in emitLoadSRsrcFromVGPRLoop()
3797 MachineBasicBlock *LoopBB = MF.CreateMachineBasicBlock(); in loadSRsrcFromVGPR() local
3802 MF.insert(MBBI, LoopBB); in loadSRsrcFromVGPR()
3805 LoopBB->addSuccessor(LoopBB); in loadSRsrcFromVGPR()
3806 LoopBB->addSuccessor(RemainderBB); in loadSRsrcFromVGPR()
3812 LoopBB->splice(LoopBB->begin(), &MBB, J); in loadSRsrcFromVGPR()
3814 MBB.addSuccessor(LoopBB); in loadSRsrcFromVGPR()
3821 MDT->addNewBlock(LoopBB, &MBB); in loadSRsrcFromVGPR()
3822 MDT->addNewBlock(RemainderBB, LoopBB); in loadSRsrcFromVGPR()
3830 emitLoadSRsrcFromVGPRLoop(TII, MRI, MBB, *LoopBB, DL, Rsrc); in loadSRsrcFromVGPR()