Lines Matching refs:InstDesc
3417 const MCInstrDesc &InstDesc = MI.getDesc(); in isOperandLegal() local
3418 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx]; in isOperandLegal()
3436 usesConstantBus(MRI, Op, InstDesc.OpInfo[i])) { in isOperandLegal()
3439 } else if (InstDesc.OpInfo[i].OperandType == AMDGPU::OPERAND_KIMM32) { in isOperandLegal()
4635 const MCInstrDesc &InstDesc = get(Opcode); in splitScalar64BitUnaryOp() local
4650 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0); in splitScalar64BitUnaryOp()
4656 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1); in splitScalar64BitUnaryOp()
4759 const MCInstrDesc &InstDesc = get(Opcode); in splitScalar64BitBinaryOp() local
4785 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0) in splitScalar64BitBinaryOp()
4790 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1) in splitScalar64BitBinaryOp()
4863 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64); in splitScalar64BitBCNT() local
4878 BuildMI(MBB, MII, DL, InstDesc, MidReg).add(SrcRegSub0).addImm(0); in splitScalar64BitBCNT()
4880 BuildMI(MBB, MII, DL, InstDesc, ResultReg).add(SrcRegSub1).addReg(MidReg); in splitScalar64BitBCNT()