Lines Matching refs:RegisterEncoding
126 } RegisterEncoding; variable
469 assert(Reg >= RegisterEncoding.VGPR0 && Reg <= RegisterEncoding.VGPRL); in getRegInterval()
470 Result.first = Reg - RegisterEncoding.VGPR0; in getRegInterval()
473 assert(Reg >= RegisterEncoding.SGPR0 && Reg < SQ_MAX_PGM_SGPRS); in getRegInterval()
474 Result.first = Reg - RegisterEncoding.SGPR0 + NUM_ALL_VGPRS; in getRegInterval()
1358 RegisterEncoding.VGPR0 = TRI->getEncodingValue(AMDGPU::VGPR0); in runOnMachineFunction()
1359 RegisterEncoding.VGPRL = in runOnMachineFunction()
1360 RegisterEncoding.VGPR0 + HardwareLimits.NumVGPRsMax - 1; in runOnMachineFunction()
1361 RegisterEncoding.SGPR0 = TRI->getEncodingValue(AMDGPU::SGPR0); in runOnMachineFunction()
1362 RegisterEncoding.SGPRL = in runOnMachineFunction()
1363 RegisterEncoding.SGPR0 + HardwareLimits.NumSGPRsMax - 1; in runOnMachineFunction()