Lines Matching refs:Ld
6367 SDValue SITargetLowering::widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const { in widenLoad() argument
6369 if (Ld->getAlignment() < 4 || Ld->isDivergent()) in widenLoad()
6373 unsigned AS = Ld->getAddressSpace(); in widenLoad()
6376 (AS != AMDGPUAS::GLOBAL_ADDRESS || !Ld->isInvariant())) in widenLoad()
6382 EVT MemVT = Ld->getMemoryVT(); in widenLoad()
6387 SDLoc SL(Ld); in widenLoad()
6389 assert((!MemVT.isVector() || Ld->getExtensionType() == ISD::NON_EXTLOAD) && in widenLoad()
6393 SDValue Ptr = Ld->getBasePtr(); in widenLoad()
6395 MVT::i32, SL, Ld->getChain(), Ptr, in widenLoad()
6396 Ld->getOffset(), in widenLoad()
6397 Ld->getPointerInfo(), MVT::i32, in widenLoad()
6398 Ld->getAlignment(), in widenLoad()
6399 Ld->getMemOperand()->getFlags(), in widenLoad()
6400 Ld->getAAInfo(), in widenLoad()
6405 assert(Ld->getExtensionType() == ISD::NON_EXTLOAD && in widenLoad()
6411 if (Ld->getExtensionType() == ISD::SEXTLOAD) { in widenLoad()
6414 } else if (Ld->getExtensionType() == ISD::ZEXTLOAD || in widenLoad()
6415 Ld->getExtensionType() == ISD::NON_EXTLOAD) { in widenLoad()
6418 assert(Ld->getExtensionType() == ISD::EXTLOAD); in widenLoad()
6421 EVT VT = Ld->getValueType(0); in widenLoad()
6428 Cvt = getLoadExtOrTrunc(DAG, Ld->getExtensionType(), Cvt, SL, IntVT); in widenLoad()