109   unsigned ScratchRsrcReg = MFI->getScratchRSrcReg();  in getReservedPrivateSegmentBufferReg()  local
110   if (ScratchRsrcReg == AMDGPU::NoRegister ||  in getReservedPrivateSegmentBufferReg()
111       !MRI.isPhysRegUsed(ScratchRsrcReg))  in getReservedPrivateSegmentBufferReg()
115       ScratchRsrcReg != TRI->reservedPrivateSegmentBufferReg(MF))  in getReservedPrivateSegmentBufferReg()
116     return ScratchRsrcReg;  in getReservedPrivateSegmentBufferReg()
139       MRI.replaceRegWith(ScratchRsrcReg, Reg);  in getReservedPrivateSegmentBufferReg()
145   return ScratchRsrcReg;  in getReservedPrivateSegmentBufferReg()
272   unsigned ScratchRsrcReg  in emitEntryFunctionPrologue()  local
283     assert(ScratchRsrcReg == AMDGPU::NoRegister);  in emitEntryFunctionPrologue()
298   bool ResourceRegUsed = ScratchRsrcReg != AMDGPU::NoRegister &&  in emitEntryFunctionPrologue()
299                          MRI.isPhysRegUsed(ScratchRsrcReg);  in emitEntryFunctionPrologue()
325       OtherBB.addLiveIn(ScratchRsrcReg);  in emitEntryFunctionPrologue()
337     ScratchRsrcReg != PreloadedPrivateBufferReg;  in emitEntryFunctionPrologue()
345     BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchRsrcReg)  in emitEntryFunctionPrologue()
357     BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchRsrcReg)  in emitEntryFunctionPrologue()
363         PreloadedPrivateBufferReg, ScratchRsrcReg);  in emitEntryFunctionPrologue()
370       unsigned ScratchRsrcReg) const {  in emitEntryFunctionScratchSetup()
380     unsigned RsrcLo = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);  in emitEntryFunctionScratchSetup()
381     unsigned RsrcHi = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);  in emitEntryFunctionScratchSetup()
382     unsigned Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);  in emitEntryFunctionScratchSetup()
389         .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchSetup()
411       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchSetup()
426     BuildMI(MBB, I, DL, LoadDwordX4, ScratchRsrcReg)  in emitEntryFunctionScratchSetup()
430       .addReg(ScratchRsrcReg, RegState::ImplicitDefine)  in emitEntryFunctionScratchSetup()
439     unsigned Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2);  in emitEntryFunctionScratchSetup()
440     unsigned Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);  in emitEntryFunctionScratchSetup()
446       unsigned Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);  in emitEntryFunctionScratchSetup()
453           .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchSetup()
471           .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchSetup()
474       unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);  in emitEntryFunctionScratchSetup()
475       unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);  in emitEntryFunctionScratchSetup()
479         .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchSetup()
483         .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchSetup()
489       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchSetup()
493       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchSetup()