Lines Matching refs:getOpcode
59 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR; in isVector()
161 if (isALUInstr(MI.getOpcode())) in canBeConsideredALU()
163 if (isVector(MI) || isCubeOp(MI.getOpcode())) in canBeConsideredALU()
165 switch (MI.getOpcode()) { in canBeConsideredALU()
185 return isTransOnly(MI.getOpcode()); in isTransOnly()
193 return isVectorOnly(MI.getOpcode()); in isVectorOnly()
207 usesVertexCache(MI.getOpcode()); in usesVertexCache()
217 usesVertexCache(MI.getOpcode())) || in usesTextureCache()
218 usesTextureCache(MI.getOpcode()); in usesTextureCache()
240 if (!isALUInstr(MI.getOpcode())) { in readsLDSSrcReg()
283 if (MI.getOpcode() == R600::DOT_4) { in getSrcs()
297 MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][0])); in getSrcs()
301 MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][1])); in getSrcs()
317 int SrcIdx = getOperandIdx(MI.getOpcode(), OpTable[j][0]); in getSrcs()
324 MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][1])); in getSrcs()
330 MI.getOperand(getOperandIdx(MI.getOpcode(), R600::OpName::literal)); in getSrcs()
549 unsigned Op = getOperandIdx(IG[i]->getOpcode(), in fitsReadPortLimitations()
615 if (!isALUInstr(MI.getOpcode())) in fitsConstReadLimitations()
658 if (isPredicateSetter(MI.getOpcode())) in findFirstPredicateSetterFrom()
689 if (isBranch(I->getOpcode())) in analyzeBranch()
691 if (!isJump(I->getOpcode())) { in analyzeBranch()
696 while (I != MBB.begin() && std::prev(I)->getOpcode() == R600::JUMP) { in analyzeBranch()
705 unsigned LastOpc = LastInst.getOpcode(); in analyzeBranch()
706 if (I == MBB.begin() || !isJump((--I)->getOpcode())) { in analyzeBranch()
712 while (!isPredicateSetter(predSet->getOpcode())) { in analyzeBranch()
726 unsigned SecondLastOpc = SecondLastInst.getOpcode(); in analyzeBranch()
731 while (!isPredicateSetter(predSet->getOpcode())) { in analyzeBranch()
750 if (It->getOpcode() == R600::CF_ALU || in FindLastAluClause()
751 It->getOpcode() == R600::CF_ALU_PUSH_BEFORE) in FindLastAluClause()
782 assert (CfAlu->getOpcode() == R600::CF_ALU); in insertBranch()
798 assert (CfAlu->getOpcode() == R600::CF_ALU); in insertBranch()
817 switch (I->getOpcode()) { in removeBranch()
827 assert (CfAlu->getOpcode() == R600::CF_ALU_PUSH_BEFORE); in removeBranch()
841 switch (I->getOpcode()) { in removeBranch()
852 assert (CfAlu->getOpcode() == R600::CF_ALU_PUSH_BEFORE); in removeBranch()
884 if (MI.getOpcode() == R600::KILLGT) { in isPredicable()
886 } else if (MI.getOpcode() == R600::CF_ALU) { in isPredicable()
969 return isPredicateSetter(MI.getOpcode()); in DefinesPredicate()
976 if (MI.getOpcode() == R600::CF_ALU) { in PredicateInstruction()
981 if (MI.getOpcode() == R600::DOT_4) { in PredicateInstruction()
1025 switch (MI.getOpcode()) { in expandPostRAPseudo()
1029 R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::addr); in expandPostRAPseudo()
1034 R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::chan); in expandPostRAPseudo()
1037 R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::dst); in expandPostRAPseudo()
1051 R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::val); in expandPostRAPseudo()
1321 assert (MI->getOpcode() == R600::DOT_4 && "Not Implemented"); in buildSlotOfVectorInstruction()
1329 getOperandIdx(MI->getOpcode(), getSlotedOps(R600::OpName::src0, Slot))); in buildSlotOfVectorInstruction()
1331 getOperandIdx(MI->getOpcode(), getSlotedOps(R600::OpName::src1, Slot))); in buildSlotOfVectorInstruction()
1351 MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(), in buildSlotOfVectorInstruction()
1358 getOperandIdx(MI->getOpcode(), getSlotedOps(Operands[i], Slot))); in buildSlotOfVectorInstruction()
1383 return getOperandIdx(MI.getOpcode(), Op); in getOperandIdx()
1404 unsigned TargetFlags = get(MI.getOpcode()).TSFlags; in getFlagOp()
1469 unsigned TargetFlags = get(MI.getOpcode()).TSFlags; in addFlag()
1490 unsigned TargetFlags = get(MI.getOpcode()).TSFlags; in clearFlag()