Lines Matching refs:MVT
58 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass); in R600TargetLowering()
59 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass); in R600TargetLowering()
60 addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass); in R600TargetLowering()
61 addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass); in R600TargetLowering()
62 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass); in R600TargetLowering()
63 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass); in R600TargetLowering()
68 setOperationAction(ISD::LOAD, MVT::i32, Custom); in R600TargetLowering()
69 setOperationAction(ISD::LOAD, MVT::v2i32, Custom); in R600TargetLowering()
70 setOperationAction(ISD::LOAD, MVT::v4i32, Custom); in R600TargetLowering()
74 for (MVT VT : MVT::integer_valuetypes()) { in R600TargetLowering()
75 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
76 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
77 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
79 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
80 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
81 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
83 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
84 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
85 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
89 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, MVT::v2i1, Expand); in R600TargetLowering()
90 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, MVT::v2i1, Expand); in R600TargetLowering()
91 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, MVT::v2i1, Expand); in R600TargetLowering()
93 setLoadExtAction(ISD::EXTLOAD, MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering()
94 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering()
95 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering()
97 setOperationAction(ISD::STORE, MVT::i8, Custom); in R600TargetLowering()
98 setOperationAction(ISD::STORE, MVT::i32, Custom); in R600TargetLowering()
99 setOperationAction(ISD::STORE, MVT::v2i32, Custom); in R600TargetLowering()
100 setOperationAction(ISD::STORE, MVT::v4i32, Custom); in R600TargetLowering()
102 setTruncStoreAction(MVT::i32, MVT::i8, Custom); in R600TargetLowering()
103 setTruncStoreAction(MVT::i32, MVT::i16, Custom); in R600TargetLowering()
106 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom); in R600TargetLowering()
107 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Custom); in R600TargetLowering()
108 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Custom); in R600TargetLowering()
109 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Custom); in R600TargetLowering()
110 setTruncStoreAction(MVT::v32i32, MVT::v32i16, Custom); in R600TargetLowering()
111 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom); in R600TargetLowering()
112 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom); in R600TargetLowering()
113 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Custom); in R600TargetLowering()
114 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Custom); in R600TargetLowering()
115 setTruncStoreAction(MVT::v32i32, MVT::v32i8, Custom); in R600TargetLowering()
118 setTruncStoreAction(MVT::v2i32, MVT::v2i1, Expand); in R600TargetLowering()
119 setTruncStoreAction(MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering()
122 setCondCodeAction(ISD::SETO, MVT::f32, Expand); in R600TargetLowering()
123 setCondCodeAction(ISD::SETUO, MVT::f32, Expand); in R600TargetLowering()
124 setCondCodeAction(ISD::SETLT, MVT::f32, Expand); in R600TargetLowering()
125 setCondCodeAction(ISD::SETLE, MVT::f32, Expand); in R600TargetLowering()
126 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand); in R600TargetLowering()
127 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); in R600TargetLowering()
128 setCondCodeAction(ISD::SETONE, MVT::f32, Expand); in R600TargetLowering()
129 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); in R600TargetLowering()
130 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand); in R600TargetLowering()
131 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); in R600TargetLowering()
132 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); in R600TargetLowering()
133 setCondCodeAction(ISD::SETULE, MVT::f32, Expand); in R600TargetLowering()
135 setCondCodeAction(ISD::SETLE, MVT::i32, Expand); in R600TargetLowering()
136 setCondCodeAction(ISD::SETLT, MVT::i32, Expand); in R600TargetLowering()
137 setCondCodeAction(ISD::SETULE, MVT::i32, Expand); in R600TargetLowering()
138 setCondCodeAction(ISD::SETULT, MVT::i32, Expand); in R600TargetLowering()
140 setOperationAction(ISD::FCOS, MVT::f32, Custom); in R600TargetLowering()
141 setOperationAction(ISD::FSIN, MVT::f32, Custom); in R600TargetLowering()
143 setOperationAction(ISD::SETCC, MVT::v4i32, Expand); in R600TargetLowering()
144 setOperationAction(ISD::SETCC, MVT::v2i32, Expand); in R600TargetLowering()
146 setOperationAction(ISD::BR_CC, MVT::i32, Expand); in R600TargetLowering()
147 setOperationAction(ISD::BR_CC, MVT::f32, Expand); in R600TargetLowering()
148 setOperationAction(ISD::BRCOND, MVT::Other, Custom); in R600TargetLowering()
150 setOperationAction(ISD::FSUB, MVT::f32, Expand); in R600TargetLowering()
152 setOperationAction(ISD::FCEIL, MVT::f64, Custom); in R600TargetLowering()
153 setOperationAction(ISD::FTRUNC, MVT::f64, Custom); in R600TargetLowering()
154 setOperationAction(ISD::FRINT, MVT::f64, Custom); in R600TargetLowering()
155 setOperationAction(ISD::FFLOOR, MVT::f64, Custom); in R600TargetLowering()
157 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in R600TargetLowering()
158 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in R600TargetLowering()
160 setOperationAction(ISD::SETCC, MVT::i32, Expand); in R600TargetLowering()
161 setOperationAction(ISD::SETCC, MVT::f32, Expand); in R600TargetLowering()
162 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom); in R600TargetLowering()
163 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Custom); in R600TargetLowering()
164 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in R600TargetLowering()
165 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); in R600TargetLowering()
167 setOperationAction(ISD::SELECT, MVT::i32, Expand); in R600TargetLowering()
168 setOperationAction(ISD::SELECT, MVT::f32, Expand); in R600TargetLowering()
169 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); in R600TargetLowering()
170 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); in R600TargetLowering()
175 setOperationAction(ISD::UADDO, MVT::i32, Custom); in R600TargetLowering()
178 setOperationAction(ISD::USUBO, MVT::i32, Custom); in R600TargetLowering()
182 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in R600TargetLowering()
184 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand); in R600TargetLowering()
185 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand); in R600TargetLowering()
188 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in R600TargetLowering()
189 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand); in R600TargetLowering()
190 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand); in R600TargetLowering()
193 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in R600TargetLowering()
194 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand); in R600TargetLowering()
195 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand); in R600TargetLowering()
197 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); in R600TargetLowering()
198 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Expand); in R600TargetLowering()
199 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Expand); in R600TargetLowering()
201 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand); in R600TargetLowering()
203 setOperationAction(ISD::FrameIndex, MVT::i32, Custom); in R600TargetLowering()
205 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Custom); in R600TargetLowering()
206 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom); in R600TargetLowering()
207 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); in R600TargetLowering()
208 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); in R600TargetLowering()
210 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom); in R600TargetLowering()
211 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom); in R600TargetLowering()
212 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in R600TargetLowering()
213 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in R600TargetLowering()
217 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); in R600TargetLowering()
218 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); in R600TargetLowering()
219 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); in R600TargetLowering()
222 setOperationAction(ISD::FMA, MVT::f32, Expand); in R600TargetLowering()
223 setOperationAction(ISD::FMA, MVT::f64, Expand); in R600TargetLowering()
229 setOperationAction(ISD::FMAD, MVT::f32, Legal); in R600TargetLowering()
233 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in R600TargetLowering()
234 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in R600TargetLowering()
238 setOperationAction(ISD::CTPOP, MVT::i32, Expand); in R600TargetLowering()
241 setOperationAction(ISD::CTPOP, MVT::i64, Expand); in R600TargetLowering()
244 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Custom); in R600TargetLowering()
247 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Custom); in R600TargetLowering()
254 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); in R600TargetLowering()
256 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 }; in R600TargetLowering()
257 for (MVT VT : ScalarIntVTs) { in R600TargetLowering()
266 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); in R600TargetLowering()
267 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); in R600TargetLowering()
270 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); in R600TargetLowering()
271 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in R600TargetLowering()
512 DAG.getConstant(0, DL, MVT::i32), // SWZ_X in LowerOperation()
513 DAG.getConstant(1, DL, MVT::i32), // SWZ_Y in LowerOperation()
514 DAG.getConstant(2, DL, MVT::i32), // SWZ_Z in LowerOperation()
515 DAG.getConstant(3, DL, MVT::i32) // SWZ_W in LowerOperation()
547 DAG.getConstant(TextureOp, DL, MVT::i32), in LowerOperation()
549 DAG.getConstant(0, DL, MVT::i32), in LowerOperation()
550 DAG.getConstant(1, DL, MVT::i32), in LowerOperation()
551 DAG.getConstant(2, DL, MVT::i32), in LowerOperation()
552 DAG.getConstant(3, DL, MVT::i32), in LowerOperation()
556 DAG.getConstant(0, DL, MVT::i32), in LowerOperation()
557 DAG.getConstant(1, DL, MVT::i32), in LowerOperation()
558 DAG.getConstant(2, DL, MVT::i32), in LowerOperation()
559 DAG.getConstant(3, DL, MVT::i32), in LowerOperation()
567 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs); in LowerOperation()
571 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
572 DAG.getConstant(0, DL, MVT::i32)), in LowerOperation()
573 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
574 DAG.getConstant(0, DL, MVT::i32)), in LowerOperation()
575 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
576 DAG.getConstant(1, DL, MVT::i32)), in LowerOperation()
577 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
578 DAG.getConstant(1, DL, MVT::i32)), in LowerOperation()
579 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
580 DAG.getConstant(2, DL, MVT::i32)), in LowerOperation()
581 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
582 DAG.getConstant(2, DL, MVT::i32)), in LowerOperation()
583 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
584 DAG.getConstant(3, DL, MVT::i32)), in LowerOperation()
585 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
586 DAG.getConstant(3, DL, MVT::i32)) in LowerOperation()
588 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args); in LowerOperation()
592 MVT PtrVT = getPointerTy(DAG.getDataLayout(), AMDGPUAS::PARAM_I_ADDRESS); in LowerOperation()
658 if (N->getValueType(0) == MVT::i1) { in ReplaceNodeResults()
667 if (N->getValueType(0) == MVT::i1) { in ReplaceNodeResults()
749 MVT ConstPtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS); in LowerGlobalAddress()
766 DAG.getConstantFP(0.15915494309, DL, MVT::f32)), in LowerTrig()
767 DAG.getConstantFP(0.5, DL, MVT::f32))); in LowerTrig()
781 DAG.getConstantFP(-0.5, DL, MVT::f32))); in LowerTrig()
786 DAG.getConstantFP(3.14159265359, DL, MVT::f32)); in LowerTrig()
874 DAG.getValueType(MVT::i1)); in LowerUADDSUBO()
886 MVT::i1, in lowerFP_TO_UINT()
887 Op, DAG.getConstantFP(1.0f, DL, MVT::f32), in lowerFP_TO_UINT()
896 MVT::i1, in lowerFP_TO_SINT()
897 Op, DAG.getConstantFP(-1.0f, DL, MVT::f32), in lowerFP_TO_SINT()
912 DAG.getConstant(ByteOffset, DL, MVT::i32), // PTR in LowerImplicitParameter()
951 if (VT == MVT::f32) { in LowerSELECT_CC()
975 ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32); in LowerSELECT_CC()
991 (CompareVT == VT || VT == MVT::i32)) { in LowerSELECT_CC()
1042 CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32); in LowerSELECT_CC()
1061 if (CompareVT == MVT::f32) { in LowerSELECT_CC()
1064 } else if (CompareVT == MVT::i32) { in LowerSELECT_CC()
1106 DAG.getConstant(SRLPad, DL, MVT::i32)); in stackPtrToRegIndex()
1143 || Store->getValue().getValueType() == MVT::i8); in lowerPrivateTruncStore()
1147 if (Store->getMemoryVT() == MVT::i8) { in lowerPrivateTruncStore()
1149 Mask = DAG.getConstant(0xff, DL, MVT::i32); in lowerPrivateTruncStore()
1150 } else if (Store->getMemoryVT() == MVT::i16) { in lowerPrivateTruncStore()
1152 Mask = DAG.getConstant(0xffff, DL, MVT::i32); in lowerPrivateTruncStore()
1167 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset); in lowerPrivateTruncStore()
1172 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateTruncStore()
1173 DAG.getConstant(0xfffffffc, DL, MVT::i32)); in lowerPrivateTruncStore()
1179 SDValue Dst = DAG.getLoad(MVT::i32, DL, Chain, Ptr, PtrInfo); in lowerPrivateTruncStore()
1184 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateTruncStore()
1185 DAG.getConstant(0x3, DL, MVT::i32)); in lowerPrivateTruncStore()
1188 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateTruncStore()
1189 DAG.getConstant(3, DL, MVT::i32)); in lowerPrivateTruncStore()
1193 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32, in lowerPrivateTruncStore()
1200 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32, in lowerPrivateTruncStore()
1204 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, Mask, ShiftAmt); in lowerPrivateTruncStore()
1208 DstMask = DAG.getNOT(DL, DstMask, MVT::i32); in lowerPrivateTruncStore()
1211 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask); in lowerPrivateTruncStore()
1214 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue); in lowerPrivateTruncStore()
1223 Chain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, NewStore); in lowerPrivateTruncStore()
1249 SDValue NewChain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, Chain); in LowerSTORE()
1274 assert(VT.bitsLE(MVT::i32)); in LowerSTORE()
1276 if (MemVT == MVT::i8) { in LowerSTORE()
1277 MaskConstant = DAG.getConstant(0xFF, DL, MVT::i32); in LowerSTORE()
1279 assert(MemVT == MVT::i16); in LowerSTORE()
1281 MaskConstant = DAG.getConstant(0xFFFF, DL, MVT::i32); in LowerSTORE()
1300 DAG.getConstant(0, DL, MVT::i32), in LowerSTORE()
1301 DAG.getConstant(0, DL, MVT::i32), in LowerSTORE()
1304 SDValue Input = DAG.getBuildVector(MVT::v4i32, DL, Src); in LowerSTORE()
1309 } else if (Ptr->getOpcode() != AMDGPUISD::DWORDADDR && VT.bitsGE(MVT::i32)) { in LowerSTORE()
1326 if (MemVT.bitsLT(MVT::i32)) in LowerSTORE()
1395 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset); in lowerPrivateExtLoad()
1400 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateExtLoad()
1401 DAG.getConstant(0xfffffffc, DL, MVT::i32)); in lowerPrivateExtLoad()
1407 SDValue Read = DAG.getLoad(MVT::i32, DL, Chain, Ptr, PtrInfo); in lowerPrivateExtLoad()
1410 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, in lowerPrivateExtLoad()
1411 LoadPtr, DAG.getConstant(0x3, DL, MVT::i32)); in lowerPrivateExtLoad()
1414 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateExtLoad()
1415 DAG.getConstant(3, DL, MVT::i32)); in lowerPrivateExtLoad()
1418 SDValue Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Read, ShiftAmt); in lowerPrivateExtLoad()
1425 Ret = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode); in lowerPrivateExtLoad()
1445 ExtType != ISD::NON_EXTLOAD && MemVT.bitsLT(MVT::i32)) { in LowerLOAD()
1472 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32, in LowerLOAD()
1473 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, in LowerLOAD()
1474 DAG.getConstant(4, DL, MVT::i32)), in LowerLOAD()
1476 AMDGPUAS::CONSTANT_BUFFER_0, DL, MVT::i32) in LowerLOAD()
1481 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in LowerLOAD()
1482 DAG.getConstant(0, DL, MVT::i32)); in LowerLOAD()
1501 assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8)); in LowerLOAD()
1518 assert(VT == MVT::i32); in LowerLOAD()
1519 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(2, DL, MVT::i32)); in LowerLOAD()
1520 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, MVT::i32, Ptr); in LowerLOAD()
1521 return DAG.getLoad(MVT::i32, DL, Chain, Ptr, LoadNode->getMemOperand()); in LowerLOAD()
1638 DAG.getConstant(PartOffset, DL, MVT::i32), DAG.getUNDEF(MVT::i32), in LowerFormalArguments()
1652 return MVT::i32; in getSetCCResultType()
1672 if (!VT.isSimple() || VT == MVT::Other) in allowsMisalignedMemoryAccesses()
1675 if (VT.bitsLT(MVT::i32)) in allowsMisalignedMemoryAccesses()
1682 return VT.bitsGT(MVT::i32) && Align % 4 == 0; in allowsMisalignedMemoryAccesses()
1707 NewBldVec[i] = DAG.getUNDEF(MVT::f32); in CompactSwizzlableVector()
1710 NewBldVec[i] = DAG.getUNDEF(MVT::f32); in CompactSwizzlableVector()
1779 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32); in OptimizeSwizzle()
1787 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32); in OptimizeSwizzle()
1802 if (LoadNode->getMemoryVT().getScalarType() != MVT::i32 || !ISD::isNON_EXTLoad(LoadNode)) in constBufferLoad()
1818 DAG.getConstant(4 * i + ConstantBlock * 16, DL, MVT::i32)); in constBufferLoad()
1819 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr); in constBufferLoad()
1821 EVT NewVT = MVT::v4i32; in constBufferLoad()
1829 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in constBufferLoad()
1830 DAG.getConstant(0, DL, MVT::i32)); in constBufferLoad()
1852 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) { in PerformDAGCombine()
1871 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS in PerformDAGCombine()
1872 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True in PerformDAGCombine()
1881 DAG.getConstant(-1, DL, MVT::i32), // True in PerformDAGCombine()
1882 DAG.getConstant(0, DL, MVT::i32), // False in PerformDAGCombine()
2086 Neg = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32); in FoldOperand()
2092 Abs = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32); in FoldOperand()
2145 Src = DAG.getRegister(R600::ALU_CONST, MVT::f32); in FoldOperand()
2153 Src = DAG.getRegister(R600::ALU_LITERAL_X, MVT::i32); in FoldOperand()
2194 Imm = DAG.getTargetConstant(ImmValue, SDLoc(ParentNode), MVT::i32); in FoldOperand()
2196 Src = DAG.getRegister(ImmReg, MVT::i32); in FoldOperand()