278       insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC),  in convertSDWAInst()
390 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {  in createRegOperand()  function in AMDGPUDisassembler
395 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,  in createRegOperand()  function in AMDGPUDisassembler
401   return createRegOperand(RegCl.getRegister(Val));  in createRegOperand()
441   return createRegOperand(SRegClassID, Val >> shift);  in createSRegOperand()
470   return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);  in decodeOperand_VGPR_32()
474   return createRegOperand(AMDGPU::VReg_64RegClassID, Val);  in decodeOperand_VReg_64()
478   return createRegOperand(AMDGPU::VReg_96RegClassID, Val);  in decodeOperand_VReg_96()
482   return createRegOperand(AMDGPU::VReg_128RegClassID, Val);  in decodeOperand_VReg_128()
706     return createRegOperand(getVgprClassId(Width), Val - VGPR_MIN);  in decodeSrcOp()
762   case 102: return createRegOperand(FLAT_SCR_LO);  in decodeSpecialReg32()
763   case 103: return createRegOperand(FLAT_SCR_HI);  in decodeSpecialReg32()
764   case 104: return createRegOperand(XNACK_MASK_LO);  in decodeSpecialReg32()
765   case 105: return createRegOperand(XNACK_MASK_HI);  in decodeSpecialReg32()
766   case 106: return createRegOperand(VCC_LO);  in decodeSpecialReg32()
767   case 107: return createRegOperand(VCC_HI);  in decodeSpecialReg32()
768   case 108: assert(!isGFX9()); return createRegOperand(TBA_LO);  in decodeSpecialReg32()
769   case 109: assert(!isGFX9()); return createRegOperand(TBA_HI);  in decodeSpecialReg32()
770   case 110: assert(!isGFX9()); return createRegOperand(TMA_LO);  in decodeSpecialReg32()
771   case 111: assert(!isGFX9()); return createRegOperand(TMA_HI);  in decodeSpecialReg32()
772   case 124: return createRegOperand(M0);  in decodeSpecialReg32()
773   case 126: return createRegOperand(EXEC_LO);  in decodeSpecialReg32()
774   case 127: return createRegOperand(EXEC_HI);  in decodeSpecialReg32()
775   case 235: return createRegOperand(SRC_SHARED_BASE);  in decodeSpecialReg32()
776   case 236: return createRegOperand(SRC_SHARED_LIMIT);  in decodeSpecialReg32()
777   case 237: return createRegOperand(SRC_PRIVATE_BASE);  in decodeSpecialReg32()
778   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);  in decodeSpecialReg32()
784   case 253: return createRegOperand(SCC);  in decodeSpecialReg32()
794   case 102: return createRegOperand(FLAT_SCR);  in decodeSpecialReg64()
795   case 104: return createRegOperand(XNACK_MASK);  in decodeSpecialReg64()
796   case 106: return createRegOperand(VCC);  in decodeSpecialReg64()
797   case 108: assert(!isGFX9()); return createRegOperand(TBA);  in decodeSpecialReg64()
798   case 110: assert(!isGFX9()); return createRegOperand(TMA);  in decodeSpecialReg64()
799   case 126: return createRegOperand(EXEC);  in decodeSpecialReg64()
815       return createRegOperand(getVgprClassId(Width),  in decodeSDWASrc()
839     return createRegOperand(getVgprClassId(Width), Val);  in decodeSDWASrc()
869     return createRegOperand(AMDGPU::VCC);  in decodeSDWAVopcDst()