Lines Matching refs:Val
396 unsigned Val) const { in createRegOperand()
398 if (Val >= RegCl.getNumRegs()) in createRegOperand()
399 return errOperand(Val, Twine(getRegClassName(RegClassID)) + in createRegOperand()
400 ": unknown register " + Twine(Val)); in createRegOperand()
401 return createRegOperand(RegCl.getRegister(Val)); in createRegOperand()
406 unsigned Val) const { in createSRegOperand()
436 if (Val % (1 << shift)) { in createSRegOperand()
438 << ": scalar reg isn't aligned " << Val; in createSRegOperand()
441 return createRegOperand(SRegClassID, Val >> shift); in createSRegOperand()
444 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { in decodeOperand_VS_32()
445 return decodeSrcOp(OPW32, Val); in decodeOperand_VS_32()
448 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { in decodeOperand_VS_64()
449 return decodeSrcOp(OPW64, Val); in decodeOperand_VS_64()
452 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { in decodeOperand_VS_128()
453 return decodeSrcOp(OPW128, Val); in decodeOperand_VS_128()
456 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { in decodeOperand_VSrc16()
457 return decodeSrcOp(OPW16, Val); in decodeOperand_VSrc16()
460 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { in decodeOperand_VSrcV216()
461 return decodeSrcOp(OPWV216, Val); in decodeOperand_VSrcV216()
464 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { in decodeOperand_VGPR_32()
468 Val &= 255; in decodeOperand_VGPR_32()
470 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); in decodeOperand_VGPR_32()
473 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { in decodeOperand_VReg_64()
474 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); in decodeOperand_VReg_64()
477 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { in decodeOperand_VReg_96()
478 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); in decodeOperand_VReg_96()
481 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { in decodeOperand_VReg_128()
482 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); in decodeOperand_VReg_128()
485 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { in decodeOperand_SReg_32()
489 return decodeSrcOp(OPW32, Val); in decodeOperand_SReg_32()
493 unsigned Val) const { in decodeOperand_SReg_32_XM0_XEXEC()
495 return decodeOperand_SReg_32(Val); in decodeOperand_SReg_32_XM0_XEXEC()
499 unsigned Val) const { in decodeOperand_SReg_32_XEXEC_HI()
501 return decodeOperand_SReg_32(Val); in decodeOperand_SReg_32_XEXEC_HI()
504 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { in decodeOperand_SReg_64()
505 return decodeSrcOp(OPW64, Val); in decodeOperand_SReg_64()
508 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { in decodeOperand_SReg_64_XEXEC()
509 return decodeSrcOp(OPW64, Val); in decodeOperand_SReg_64_XEXEC()
512 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { in decodeOperand_SReg_128()
513 return decodeSrcOp(OPW128, Val); in decodeOperand_SReg_128()
516 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { in decodeOperand_SReg_256()
517 return decodeDstOp(OPW256, Val); in decodeOperand_SReg_256()
520 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { in decodeOperand_SReg_512()
521 return decodeDstOp(OPW512, Val); in decodeOperand_SReg_512()
691 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { in getTTmpIdx()
697 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; in getTTmpIdx()
700 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const { in decodeSrcOp()
703 assert(Val < 512); // enum9 in decodeSrcOp()
705 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { in decodeSrcOp()
706 return createRegOperand(getVgprClassId(Width), Val - VGPR_MIN); in decodeSrcOp()
708 if (Val <= SGPR_MAX) { in decodeSrcOp()
710 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); in decodeSrcOp()
713 int TTmpIdx = getTTmpIdx(Val); in decodeSrcOp()
718 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) in decodeSrcOp()
719 return decodeIntImmed(Val); in decodeSrcOp()
721 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) in decodeSrcOp()
722 return decodeFPImmed(Width, Val); in decodeSrcOp()
724 if (Val == LITERAL_CONST) in decodeSrcOp()
731 return decodeSpecialReg32(Val); in decodeSrcOp()
733 return decodeSpecialReg64(Val); in decodeSrcOp()
739 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { in decodeDstOp()
742 assert(Val < 128); in decodeDstOp()
745 if (Val <= SGPR_MAX) { in decodeDstOp()
747 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); in decodeDstOp()
750 int TTmpIdx = getTTmpIdx(Val); in decodeDstOp()
758 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { in decodeSpecialReg32()
761 switch (Val) { in decodeSpecialReg32()
787 return errOperand(Val, "unknown operand encoding " + Twine(Val)); in decodeSpecialReg32()
790 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { in decodeSpecialReg64()
793 switch (Val) { in decodeSpecialReg64()
802 return errOperand(Val, "unknown operand encoding " + Twine(Val)); in decodeSpecialReg64()
806 const unsigned Val) const { in decodeSDWASrc()
813 if (SDWA9EncValues::SRC_VGPR_MIN <= static_cast<int>(Val) && in decodeSDWASrc()
814 Val <= SDWA9EncValues::SRC_VGPR_MAX) { in decodeSDWASrc()
816 Val - SDWA9EncValues::SRC_VGPR_MIN); in decodeSDWASrc()
818 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && in decodeSDWASrc()
819 Val <= SDWA9EncValues::SRC_SGPR_MAX) { in decodeSDWASrc()
821 Val - SDWA9EncValues::SRC_SGPR_MIN); in decodeSDWASrc()
823 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && in decodeSDWASrc()
824 Val <= SDWA9EncValues::SRC_TTMP_MAX) { in decodeSDWASrc()
826 Val - SDWA9EncValues::SRC_TTMP_MIN); in decodeSDWASrc()
829 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; in decodeSDWASrc()
839 return createRegOperand(getVgprClassId(Width), Val); in decodeSDWASrc()
844 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { in decodeSDWASrc16()
845 return decodeSDWASrc(OPW16, Val); in decodeSDWASrc16()
848 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { in decodeSDWASrc32()
849 return decodeSDWASrc(OPW32, Val); in decodeSDWASrc32()
852 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { in decodeSDWAVopcDst()
857 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { in decodeSDWAVopcDst()
858 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; in decodeSDWAVopcDst()
860 int TTmpIdx = getTTmpIdx(Val); in decodeSDWAVopcDst()
863 } else if (Val > AMDGPU::EncValues::SGPR_MAX) { in decodeSDWAVopcDst()
864 return decodeSpecialReg64(Val); in decodeSDWAVopcDst()
866 return createSRegOperand(getSgprClassId(OPW64), Val); in decodeSDWAVopcDst()
902 [Value](const SymbolInfoTy& Val) { in tryAddingSymbolicOperand() argument
903 return std::get<0>(Val) == static_cast<uint64_t>(Value) in tryAddingSymbolicOperand()
904 && std::get<2>(Val) == ELF::STT_NOTYPE; in tryAddingSymbolicOperand()