891   void cvtMubufImpl(MCInst &Inst, const OperandVector &Operands,
893   void cvtDSImpl(MCInst &Inst, const OperandVector &Operands,
1023                                OperandVector &Operands, MCStreamer &Out,
1027   OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Mnemonic);
1030                         SMLoc NameLoc, OperandVector &Operands) override;
1036   parseIntWithPrefix(const char *Prefix, OperandVector &Operands,
1042     OperandVector &Operands,
1047   parseNamedBit(const char *Name, OperandVector &Operands,
1053   OperandMatchResultTy parseImm(OperandVector &Operands, bool AbsMod = false);
1054   OperandMatchResultTy parseReg(OperandVector &Operands);
1055   OperandMatchResultTy parseRegOrImm(OperandVector &Operands, bool AbsMod = false);
1056   OperandMatchResultTy parseRegOrImmWithFPInputMods(OperandVector &Operands, bool AllowImm = true);
1057   OperandMatchResultTy parseRegOrImmWithIntInputMods(OperandVector &Operands, bool AllowImm = true);
1058   OperandMatchResultTy parseRegWithFPInputMods(OperandVector &Operands);
1059   OperandMatchResultTy parseRegWithIntInputMods(OperandVector &Operands);
1060   OperandMatchResultTy parseVReg32OrOff(OperandVector &Operands);
1061   OperandMatchResultTy parseDfmtNfmt(OperandVector &Operands);
1063   void cvtDSOffset01(MCInst &Inst, const OperandVector &Operands);
1064   void cvtDS(MCInst &Inst, const OperandVector &Operands) { cvtDSImpl(Inst, Operands, false); }  in cvtDS()  argument
1065   void cvtDSGds(MCInst &Inst, const OperandVector &Operands) { cvtDSImpl(Inst, Operands, true); }  in cvtDSGds()  argument
1066   void cvtExp(MCInst &Inst, const OperandVector &Operands);
1069   OperandMatchResultTy parseSWaitCntOps(OperandVector &Operands);
1070   OperandMatchResultTy parseHwreg(OperandVector &Operands);
1105   OperandMatchResultTy parseOptionalOperand(OperandVector &Operands);
1106   OperandMatchResultTy parseOptionalOpr(OperandVector &Operands);
1108   OperandMatchResultTy parseExpTgt(OperandVector &Operands);
1109   OperandMatchResultTy parseSendMsgOp(OperandVector &Operands);
1110   OperandMatchResultTy parseInterpSlot(OperandVector &Operands);
1111   OperandMatchResultTy parseInterpAttr(OperandVector &Operands);
1112   OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands);
1118   OperandMatchResultTy parseSwizzleOp(OperandVector &Operands);
1127 …void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false, f…  in cvtMubuf()  argument
1128 …void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, tr…  in cvtMubufAtomic()  argument
1129 … cvtMubufAtomicReturn(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, …  in cvtMubufAtomicReturn()  argument
1130 …void cvtMubufLds(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false…  in cvtMubufLds()  argument
1131   void cvtMtbuf(MCInst &Inst, const OperandVector &Operands);
1142   OperandMatchResultTy parseOModOperand(OperandVector &Operands);
1144   void cvtVOP3(MCInst &Inst, const OperandVector &Operands,
1146   void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands);
1147   void cvtVOP3(MCInst &Inst, const OperandVector &Operands);
1148   void cvtVOP3P(MCInst &Inst, const OperandVector &Operands);
1150   void cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands);
1152   void cvtMIMG(MCInst &Inst, const OperandVector &Operands,
1154   void cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands);
1156   OperandMatchResultTy parseDPPCtrl(OperandVector &Operands);
1160   void cvtDPP(MCInst &Inst, const OperandVector &Operands);
1162   OperandMatchResultTy parseSDWASel(OperandVector &Operands, StringRef Prefix,
1164   OperandMatchResultTy parseSDWADstUnused(OperandVector &Operands);
1165   void cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands);
1166   void cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands);
1167   void cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands);
1168   void cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands);
1169   void cvtSDWA(MCInst &Inst, const OperandVector &Operands,
1897 AMDGPUAsmParser::parseImm(OperandVector &Operands, bool AbsMod) {  in parseImm()  argument
1918     Operands.push_back(AMDGPUOperand::CreateImm(this, IntVal, S));  in parseImm()
1929     Operands.push_back(  in parseImm()
1940 AMDGPUAsmParser::parseReg(OperandVector &Operands) {  in parseReg()  argument
1944     Operands.push_back(std::move(R));  in parseReg()
1951 AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands, bool AbsMod) {  in parseRegOrImm()  argument
1952   auto res = parseImm(Operands, AbsMod);  in parseRegOrImm()
1957   return parseReg(Operands);  in parseRegOrImm()
1961 AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands,  in parseRegOrImmWithFPInputMods()  argument
2025     Res = parseRegOrImm(Operands, Abs);  in parseRegOrImmWithFPInputMods()
2027     Res = parseReg(Operands);  in parseRegOrImmWithFPInputMods()
2063     AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());  in parseRegOrImmWithFPInputMods()
2070 AMDGPUAsmParser::parseRegOrImmWithIntInputMods(OperandVector &Operands,  in parseRegOrImmWithIntInputMods()  argument
2087     Res = parseRegOrImm(Operands);  in parseRegOrImmWithIntInputMods()
2089     Res = parseReg(Operands);  in parseRegOrImmWithIntInputMods()
2106     AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());  in parseRegOrImmWithIntInputMods()
2114 AMDGPUAsmParser::parseRegWithFPInputMods(OperandVector &Operands) {  in parseRegWithFPInputMods()  argument
2115   return parseRegOrImmWithFPInputMods(Operands, false);  in parseRegWithFPInputMods()
2119 AMDGPUAsmParser::parseRegWithIntInputMods(OperandVector &Operands) {  in parseRegWithIntInputMods()  argument
2120   return parseRegOrImmWithIntInputMods(Operands, false);  in parseRegWithIntInputMods()
2123 OperandMatchResultTy AMDGPUAsmParser::parseVReg32OrOff(OperandVector &Operands) {  in parseVReg32OrOff()  argument
2126     Operands.push_back(std::move(Reg));  in parseVReg32OrOff()
2132     Operands.push_back(AMDGPUOperand::CreateImm(this, 0, Tok.getLoc(),  in parseVReg32OrOff()
2510                                               OperandVector &Operands,  in MatchAndEmitInstruction()  argument
2518     auto R = MatchInstructionImpl(Operands, Inst, EI, MatchingInlineAsm,  in MatchAndEmitInstruction()
2554         ((AMDGPUOperand &)*Operands[0]).getToken(), FBS);  in MatchAndEmitInstruction()
2556                  ((AMDGPUOperand &)*Operands[0]).getLocRange());  in MatchAndEmitInstruction()
2562       if (ErrorInfo >= Operands.size()) {  in MatchAndEmitInstruction()
2565       ErrorLoc = ((AMDGPUOperand &)*Operands[ErrorInfo]).getStartLoc();  in MatchAndEmitInstruction()
3244 AMDGPUAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {  in parseOperand()  argument
3246   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);  in parseOperand()
3258   ResTy = parseRegOrImm(Operands);  in parseOperand()
3268     Operands.push_back(AMDGPUOperand::CreateExpr(this, Expr, S));  in parseOperand()
3274     Operands.push_back(AMDGPUOperand::CreateToken(this, Tok.getString(), S));  in parseOperand()
3306                                        SMLoc NameLoc, OperandVector &Operands) {  in ParseInstruction()  argument
3309   Operands.push_back(AMDGPUOperand::CreateToken(this, Name, NameLoc));  in ParseInstruction()
3312     OperandMatchResultTy Res = parseOperand(Operands, Name);  in ParseInstruction()
3379 AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, OperandVector &Operands,  in parseIntWithPrefix()  argument
3393   Operands.push_back(AMDGPUOperand::CreateImm(this, Value, S, ImmTy));  in parseIntWithPrefix()
3399   OperandVector &Operands,  in parseOperandArrayWithPrefix()  argument
3443   Operands.push_back(AMDGPUOperand::CreateImm(this, Val, S, ImmTy));  in parseOperandArrayWithPrefix()
3448 AMDGPUAsmParser::parseNamedBit(const char *Name, OperandVector &Operands,  in parseNamedBit()  argument
3479   Operands.push_back(AMDGPUOperand::CreateImm(this, Bit, S, ImmTy));  in parseNamedBit()
3484   MCInst& Inst, const OperandVector& Operands,  in addOptionalImmOperand()  argument
3491     ((AMDGPUOperand &)*Operands[Idx]).addImmOperands(Inst, 1);  in addOptionalImmOperand()
3524 AMDGPUAsmParser::parseDfmtNfmt(OperandVector &Operands) {  in parseDfmtNfmt()  argument
3563   Operands.push_back(  in parseDfmtNfmt()
3573                                     const OperandVector &Operands) {  in cvtDSOffset01()  argument
3576   for (unsigned i = 1, e = Operands.size(); i != e; ++i) {  in cvtDSOffset01()
3577     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);  in cvtDSOffset01()
3589   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset0);  in cvtDSOffset01()
3590   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset1);  in cvtDSOffset01()
3591   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGDS);  in cvtDSOffset01()
3596 void AMDGPUAsmParser::cvtDSImpl(MCInst &Inst, const OperandVector &Operands,  in cvtDSImpl()  argument
3600   for (unsigned i = 1, e = Operands.size(); i != e; ++i) {  in cvtDSImpl()
3601     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);  in cvtDSImpl()
3623   addOptionalImmOperand(Inst, Operands, OptionalIdx, OffsetType);  in cvtDSImpl()
3626     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGDS);  in cvtDSImpl()
3631 void AMDGPUAsmParser::cvtExp(MCInst &Inst, const OperandVector &Operands) {  in cvtExp()  argument
3638   for (unsigned i = 1, e = Operands.size(); i != e; ++i) {  in cvtExp()
3639     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);  in cvtExp()
3686   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpVM);  in cvtExp()
3687   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpCompr);  in cvtExp()
3768 AMDGPUAsmParser::parseSWaitCntOps(OperandVector &Operands) {  in parseSWaitCntOps()  argument
3788   Operands.push_back(AMDGPUOperand::CreateImm(this, Waitcnt, S));  in parseSWaitCntOps()
3857 OperandMatchResultTy AMDGPUAsmParser::parseHwreg(OperandVector &Operands) {  in parseHwreg()  argument
3896   Operands.push_back(AMDGPUOperand::CreateImm(this, Imm16Val, S, AMDGPUOperand::ImmTyHwreg));  in parseHwreg()
4004 OperandMatchResultTy AMDGPUAsmParser::parseInterpSlot(OperandVector &Operands) {  in parseInterpSlot()  argument
4020   Operands.push_back(AMDGPUOperand::CreateImm(this, Slot, S,  in parseInterpSlot()
4025 OperandMatchResultTy AMDGPUAsmParser::parseInterpAttr(OperandVector &Operands) {  in parseInterpAttr()  argument
4058   Operands.push_back(AMDGPUOperand::CreateImm(this, Attr, S,  in parseInterpAttr()
4060   Operands.push_back(AMDGPUOperand::CreateImm(this, AttrChan, SChan,  in parseInterpAttr()
4128 OperandMatchResultTy AMDGPUAsmParser::parseExpTgt(OperandVector &Operands) {  in parseExpTgt()  argument
4139   Operands.push_back(AMDGPUOperand::CreateImm(this, Val, S,  in parseExpTgt()
4145 AMDGPUAsmParser::parseSendMsgOp(OperandVector &Operands) {  in parseSendMsgOp()  argument
4219   Operands.push_back(AMDGPUOperand::CreateImm(this, Imm16Val, S, AMDGPUOperand::ImmTySendMsg));  in parseSendMsgOp()
4491 AMDGPUAsmParser::parseSwizzleOp(OperandVector &Operands) {  in parseSwizzleOp()  argument
4506     Operands.push_back(AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTySwizzle));  in parseSwizzleOp()
4512     return parseOptionalOpr(Operands);  in parseSwizzleOp()
4526 AMDGPUAsmParser::parseSOppBrTarget(OperandVector &Operands) {  in parseSOppBrTarget()  argument
4535       Operands.push_back(AMDGPUOperand::CreateImm(this, Imm, S));  in parseSOppBrTarget()
4540       Operands.push_back(AMDGPUOperand::CreateExpr(this,  in parseSOppBrTarget()
4561                                const OperandVector &Operands,  in cvtMubufImpl()  argument
4570   for (unsigned i = 1, e = Operands.size(); i != e; ++i) {  in cvtMubufImpl()
4571     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);  in cvtMubufImpl()
4619   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset);  in cvtMubufImpl()
4621     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);  in cvtMubufImpl()
4623   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC);  in cvtMubufImpl()
4626     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);  in cvtMubufImpl()
4630 void AMDGPUAsmParser::cvtMtbuf(MCInst &Inst, const OperandVector &Operands) {  in cvtMtbuf()  argument
4633   for (unsigned i = 1, e = Operands.size(); i != e; ++i) {  in cvtMtbuf()
4634     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);  in cvtMtbuf()
4659   addOptionalImmOperand(Inst, Operands, OptionalIdx,  in cvtMtbuf()
4661   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyFORMAT);  in cvtMtbuf()
4662   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);  in cvtMtbuf()
4663   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC);  in cvtMtbuf()
4664   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);  in cvtMtbuf()
4671 void AMDGPUAsmParser::cvtMIMG(MCInst &Inst, const OperandVector &Operands,  in cvtMIMG()  argument
4676     ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);  in cvtMIMG()
4682     ((AMDGPUOperand &)*Operands[I - 1]).addRegOperands(Inst, 1);  in cvtMIMG()
4687   for (unsigned E = Operands.size(); I != E; ++I) {  in cvtMIMG()
4688     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);  in cvtMIMG()
4700   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDMask);  in cvtMIMG()
4701   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyUNorm);  in cvtMIMG()
4702   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);  in cvtMIMG()
4703   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC);  in cvtMIMG()
4704   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyR128A16);  in cvtMIMG()
4705   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);  in cvtMIMG()
4706   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyLWE);  in cvtMIMG()
4707   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDA);  in cvtMIMG()
4708   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyD16);  in cvtMIMG()
4711 void AMDGPUAsmParser::cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands) {  in cvtMIMGAtomic()  argument
4712   cvtMIMG(Inst, Operands, true);  in cvtMIMGAtomic()
4834 OperandMatchResultTy AMDGPUAsmParser::parseOptionalOperand(OperandVector &Operands) {  in parseOptionalOperand()  argument
4835   unsigned size = Operands.size();  in parseOptionalOperand()
4838   OperandMatchResultTy res = parseOptionalOpr(Operands);  in parseOptionalOperand()
4851   if (size == 1 || ((AMDGPUOperand &)*Operands[size - 1]).isRegKind()) {  in parseOptionalOperand()
4860       res = parseOptionalOpr(Operands);  in parseOptionalOperand()
4867 OperandMatchResultTy AMDGPUAsmParser::parseOptionalOpr(OperandVector &Operands) {  in parseOptionalOpr()  argument
4872       res = parseNamedBit(Op.Name, Operands, Op.Type);  in parseOptionalOpr()
4874       res = parseOModOperand(Operands);  in parseOptionalOpr()
4878       res = parseSDWASel(Operands, Op.Name, Op.Type);  in parseOptionalOpr()
4880       res = parseSDWADstUnused(Operands);  in parseOptionalOpr()
4885       res = parseOperandArrayWithPrefix(Op.Name, Operands, Op.Type,  in parseOptionalOpr()
4888       res = parseDfmtNfmt(Operands);  in parseOptionalOpr()
4890       res = parseIntWithPrefix(Op.Name, Operands, Op.Type, Op.ConvertResult);  in parseOptionalOpr()
4899 OperandMatchResultTy AMDGPUAsmParser::parseOModOperand(OperandVector &Operands) {  in parseOModOperand()  argument
4902     return parseIntWithPrefix("mul", Operands,  in parseOModOperand()
4907     return parseIntWithPrefix("div", Operands,  in parseOModOperand()
4914 void AMDGPUAsmParser::cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands) {  in cvtVOP3OpSel()  argument
4915   cvtVOP3P(Inst, Operands);  in cvtVOP3OpSel()
4949 void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands)  in cvtVOP3Interp()  argument
4957     ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);  in cvtVOP3Interp()
4960   for (unsigned E = Operands.size(); I != E; ++I) {  in cvtVOP3Interp()
4961     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);  in cvtVOP3Interp()
4976     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyHigh);  in cvtVOP3Interp()
4980     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);  in cvtVOP3Interp()
4984     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);  in cvtVOP3Interp()
4988 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands,  in cvtVOP3()  argument
4995     ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);  in cvtVOP3()
5000     for (unsigned E = Operands.size(); I != E; ++I) {  in cvtVOP3()
5001       AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);  in cvtVOP3()
5014     for (unsigned E = Operands.size(); I != E; ++I) {  in cvtVOP3()
5015       AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);  in cvtVOP3()
5025     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);  in cvtVOP3()
5029     addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);  in cvtVOP3()
5048 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {  in cvtVOP3()  argument
5050   cvtVOP3(Inst, Operands, OptionalIdx);  in cvtVOP3()
5054                                const OperandVector &Operands) {  in cvtVOP3P()  argument
5061   cvtVOP3(Inst, Operands, OptIdx);  in cvtVOP3P()
5071   addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSel);  in cvtVOP3P()
5076     addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSelHi,  in cvtVOP3P()
5083     addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegLo);  in cvtVOP3P()
5084     addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegHi);  in cvtVOP3P()
5175 AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) {  in parseDPPCtrl()  argument
5271   Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, AMDGPUOperand::ImmTyDppCtrl));  in parseDPPCtrl()
5287 void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands) {  in cvtDPP()  argument
5293     ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);  in cvtDPP()
5296   for (unsigned E = Operands.size(); I != E; ++I) {  in cvtDPP()
5304     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);  in cvtDPP()
5322   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf);  in cvtDPP()
5323   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf);  in cvtDPP()
5324   addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl);  in cvtDPP()
5332 AMDGPUAsmParser::parseSDWASel(OperandVector &Operands, StringRef Prefix,  in parseSDWASel()  argument
5361   Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, Type));  in parseSDWASel()
5366 AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) {  in parseSDWADstUnused()  argument
5390   Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, AMDGPUOperand::ImmTySdwaDstUnused));  in parseSDWADstUnused()
5394 void AMDGPUAsmParser::cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands) {  in cvtSdwaVOP1()  argument
5395   cvtSDWA(Inst, Operands, SIInstrFlags::VOP1);  in cvtSdwaVOP1()
5398 void AMDGPUAsmParser::cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands) {  in cvtSdwaVOP2()  argument
5399   cvtSDWA(Inst, Operands, SIInstrFlags::VOP2);  in cvtSdwaVOP2()
5402 void AMDGPUAsmParser::cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands) {  in cvtSdwaVOP2b()  argument
5403   cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, true);  in cvtSdwaVOP2b()
5406 void AMDGPUAsmParser::cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands) {  in cvtSdwaVOPC()  argument
5407   cvtSDWA(Inst, Operands, SIInstrFlags::VOPC, isVI());  in cvtSdwaVOPC()
5410 void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,  in cvtSDWA()  argument
5420     ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);  in cvtSDWA()
5423   for (unsigned E = Operands.size(); I != E; ++I) {  in cvtSDWA()
5424     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);  in cvtSDWA()
5456       addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);  in cvtSDWA()
5458         addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI, 0);  in cvtSDWA()
5460 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstSel, SdwaSel::DWORD);  in cvtSDWA()
5461 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstUnused, DstUnused::U…  in cvtSDWA()
5462 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD…  in cvtSDWA()
5466       addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);  in cvtSDWA()
5468         addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI, 0);  in cvtSDWA()
5470 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstSel, SdwaSel::DWORD);  in cvtSDWA()
5471 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstUnused, DstUnused::U…  in cvtSDWA()
5472 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD…  in cvtSDWA()
5473 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, SdwaSel::DWORD…  in cvtSDWA()
5477       addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);  in cvtSDWA()
5478 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD…  in cvtSDWA()
5479 …addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, SdwaSel::DWORD…  in cvtSDWA()