Lines Matching refs:SDValue
37 SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
40 static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
41 static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
44 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
45 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
49 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
51 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
52 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
53 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
55 SDValue LowerFROUND32_16(SDValue Op, SelectionDAG &DAG) const;
56 SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
57 SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
58 SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
59 SDValue LowerFLOG(SDValue Op, SelectionDAG &DAG,
61 SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const;
63 SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const;
65 SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
66 SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
67 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
68 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
70 SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
71 SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
72 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
73 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
75 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
79 SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
80 SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
81 SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const;
83 SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL,
84 unsigned Opc, SDValue LHS,
86 SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
87 SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
88 SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
89 SDValue performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) const;
90 SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
91 SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
92 SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const;
93 SDValue performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) const;
94 SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
95 SDValue RHS, DAGCombinerInfo &DCI) const;
96 SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
98 bool isConstantCostlierToNegate(SDValue N) const;
99 SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
100 SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
101 SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
105 virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
109 std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
111 SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
112 SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
115 SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
118 SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
120 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
121 SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
122 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
123 SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
124 void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
125 SmallVectorImpl<SDValue> &Results) const;
134 bool mayIgnoreSignedZero(SDValue Op) const { in mayIgnoreSignedZero()
145 static inline SDValue stripBitcast(SDValue Val) { in stripBitcast()
158 bool isZExtFree(SDValue Val, EVT VT2) const override;
184 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
186 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
189 SDValue addTokenForArgument(SDValue Chain,
194 SDValue lowerUnhandledCall(CallLoweringInfo &CLI,
195 SmallVectorImpl<SDValue> &InVals,
197 SDValue LowerCall(CallLoweringInfo &CLI,
198 SmallVectorImpl<SDValue> &InVals) const override;
200 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op,
203 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
204 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
206 SmallVectorImpl<SDValue> &Results,
209 SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
210 SDValue RHS, SDValue True, SDValue False,
211 SDValue CC, DAGCombinerInfo &DCI) const;
225 bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override { in isFsqrtCheap()
228 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
231 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
240 void computeKnownBitsForTargetNode(const SDValue Op,
246 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
250 bool isKnownNeverNaNForTargetNode(SDValue Op,
260 SDValue CreateLiveInRegister(SelectionDAG &DAG,
265 SDValue CreateLiveInRegister(SelectionDAG &DAG, in CreateLiveInRegister()
272 SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG, in CreateLiveInRegisterRaw()
280 SDValue loadStackInputValue(SelectionDAG &DAG,
285 SDValue storeStackInputValue(SelectionDAG &DAG,
287 SDValue Chain,
288 SDValue ArgVal,
291 SDValue loadInputValue(SelectionDAG &DAG,