835 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {  in isNarrowingProfitable()  argument
842   return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;  in isNarrowingProfitable()
2642   EVT SrcVT = Src.getValueType();  in LowerFP_TO_SINT()  local
2643   if (Subtarget->has16BitInsts() && SrcVT == MVT::f16) {  in LowerFP_TO_SINT()
2665   EVT SrcVT = Src.getValueType();  in LowerFP_TO_UINT()  local
2666   if (Subtarget->has16BitInsts() && SrcVT == MVT::f16) {  in LowerFP_TO_UINT()
2913     EVT SrcVT = Src.getValueType();  in performAssertSZExtCombine()  local
2914     if (SrcVT.bitsGE(ExtVT)) {  in performAssertSZExtCombine()
2915       SDValue NewInReg = DAG.getNode(N->getOpcode(), SL, SrcVT, Src, N1);  in performAssertSZExtCombine()
3136     EVT SrcVT = Src.getValueType();  in performTruncateCombine()  local
3137     if (SrcVT.getScalarSizeInBits() > 32 &&  in performTruncateCombine()
3733     EVT SrcVT = Src.getValueType();  in performFNegCombine()  local
3736     SDValue IntFNeg = DAG.getNode(ISD::XOR, SL, SrcVT, Src,  in performFNegCombine()
3737                                   DAG.getConstant(0x8000, SL, SrcVT));  in performFNegCombine()
3758     EVT SrcVT = Src.getValueType();  in performFAbsCombine()  local
3761     SDValue IntFAbs = DAG.getNode(ISD::AND, SL, SrcVT, Src,  in performFAbsCombine()
3762                                   DAG.getConstant(0x7fff, SL, SrcVT));  in performFAbsCombine()
3801         EVT SrcVT = Src.getValueType();  in PerformDAGCombine()  local
3804         if (SrcVT.getVectorNumElements() == NElts) {  in PerformDAGCombine()
3809           for (unsigned I = 0, E = SrcVT.getVectorNumElements(); I != E; ++I) {  in PerformDAGCombine()