Lines Matching refs:SL
1244 SDLoc SL(Op); in LowerCONCAT_VECTORS() local
1245 SDValue Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(0)); in LowerCONCAT_VECTORS()
1246 SDValue Hi = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(1)); in LowerCONCAT_VECTORS()
1248 SDValue BV = DAG.getBuildVector(MVT::v2i32, SL, { Lo, Hi }); in LowerCONCAT_VECTORS()
1249 return DAG.getNode(ISD::BITCAST, SL, VT, BV); in LowerCONCAT_VECTORS()
1346 SDLoc SL(Op); in split64BitValue() local
1348 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in split64BitValue()
1350 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in split64BitValue()
1351 const SDValue One = DAG.getConstant(1, SL, MVT::i32); in split64BitValue()
1353 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in split64BitValue()
1354 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in split64BitValue()
1360 SDLoc SL(Op); in getLoHalf64() local
1362 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in getLoHalf64()
1363 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in getLoHalf64()
1364 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in getLoHalf64()
1368 SDLoc SL(Op); in getHiHalf64() local
1370 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in getHiHalf64()
1371 const SDValue One = DAG.getConstant(1, SL, MVT::i32); in getHiHalf64()
1372 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in getHiHalf64()
1388 SDLoc SL(Op); in SplitVectorLoad() local
1398 std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT); in SplitVectorLoad()
1404 SDValue LoLoad = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT, in SplitVectorLoad()
1407 SDValue HiPtr = DAG.getObjectPtrOffset(SL, BasePtr, Size); in SplitVectorLoad()
1409 DAG.getExtLoad(Load->getExtensionType(), SL, HiVT, Load->getChain(), in SplitVectorLoad()
1414 DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad), in SplitVectorLoad()
1415 DAG.getNode(ISD::TokenFactor, SL, MVT::Other, in SplitVectorLoad()
1419 return DAG.getMergeValues(Ops, SL); in SplitVectorLoad()
1436 SDLoc SL(Op); in SplitVectorStore() local
1444 std::tie(Lo, Hi) = DAG.SplitVector(Val, SL, LoVT, HiVT); in SplitVectorStore()
1446 SDValue HiPtr = DAG.getObjectPtrOffset(SL, BasePtr, LoMemVT.getStoreSize()); in SplitVectorStore()
1454 DAG.getTruncStore(Chain, SL, Lo, BasePtr, SrcValue, LoMemVT, BaseAlign, in SplitVectorStore()
1457 DAG.getTruncStore(Chain, SL, Hi, HiPtr, SrcValue.getWithOffset(Size), in SplitVectorStore()
1460 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore); in SplitVectorStore()
1959 SDLoc SL(Op); in LowerFREM() local
1966 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y); in LowerFREM()
1967 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div); in LowerFREM()
1968 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y); in LowerFREM()
1970 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul); in LowerFREM()
1974 SDLoc SL(Op); in LowerFCEIL() local
1981 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFCEIL()
1983 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64); in LowerFCEIL()
1984 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64); in LowerFCEIL()
1989 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT); in LowerFCEIL()
1990 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE); in LowerFCEIL()
1991 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc); in LowerFCEIL()
1993 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero); in LowerFCEIL()
1995 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFCEIL()
1998 static SDValue extractF64Exponent(SDValue Hi, const SDLoc &SL, in extractF64Exponent() argument
2003 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32, in extractF64Exponent()
2005 DAG.getConstant(FractBits - 32, SL, MVT::i32), in extractF64Exponent()
2006 DAG.getConstant(ExpBits, SL, MVT::i32)); in extractF64Exponent()
2007 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart, in extractF64Exponent()
2008 DAG.getConstant(1023, SL, MVT::i32)); in extractF64Exponent()
2014 SDLoc SL(Op); in LowerFTRUNC() local
2019 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in LowerFTRUNC()
2020 const SDValue One = DAG.getConstant(1, SL, MVT::i32); in LowerFTRUNC()
2022 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src); in LowerFTRUNC()
2026 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One); in LowerFTRUNC()
2028 SDValue Exp = extractF64Exponent(Hi, SL, DAG); in LowerFTRUNC()
2033 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, SL, MVT::i32); in LowerFTRUNC()
2034 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask); in LowerFTRUNC()
2037 SDValue SignBit64 = DAG.getBuildVector(MVT::v2i32, SL, {Zero, SignBit}); in LowerFTRUNC()
2038 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64); in LowerFTRUNC()
2040 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src); in LowerFTRUNC()
2042 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, SL, MVT::i64); in LowerFTRUNC()
2044 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp); in LowerFTRUNC()
2045 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64); in LowerFTRUNC()
2046 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not); in LowerFTRUNC()
2051 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, SL, MVT::i32); in LowerFTRUNC()
2053 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT); in LowerFTRUNC()
2054 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT); in LowerFTRUNC()
2056 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0); in LowerFTRUNC()
2057 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1); in LowerFTRUNC()
2059 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2); in LowerFTRUNC()
2063 SDLoc SL(Op); in LowerFRINT() local
2069 SDValue C1 = DAG.getConstantFP(C1Val, SL, MVT::f64); in LowerFRINT()
2070 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src); in LowerFRINT()
2074 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign); in LowerFRINT()
2075 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign); in LowerFRINT()
2077 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src); in LowerFRINT()
2080 SDValue C2 = DAG.getConstantFP(C2Val, SL, MVT::f64); in LowerFRINT()
2084 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT); in LowerFRINT()
2086 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2); in LowerFRINT()
2102 SDLoc SL(Op); in LowerFROUND32_16() local
2106 SDValue T = DAG.getNode(ISD::FTRUNC, SL, VT, X); in LowerFROUND32_16()
2110 SDValue Diff = DAG.getNode(ISD::FSUB, SL, VT, X, T); in LowerFROUND32_16()
2112 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, VT, Diff); in LowerFROUND32_16()
2114 const SDValue Zero = DAG.getConstantFP(0.0, SL, VT); in LowerFROUND32_16()
2115 const SDValue One = DAG.getConstantFP(1.0, SL, VT); in LowerFROUND32_16()
2116 const SDValue Half = DAG.getConstantFP(0.5, SL, VT); in LowerFROUND32_16()
2118 SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, VT, One, X); in LowerFROUND32_16()
2123 SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE); in LowerFROUND32_16()
2125 SDValue Sel = DAG.getNode(ISD::SELECT, SL, VT, Cmp, SignOne, Zero); in LowerFROUND32_16()
2127 return DAG.getNode(ISD::FADD, SL, VT, T, Sel); in LowerFROUND32_16()
2131 SDLoc SL(Op); in LowerFROUND64() local
2134 SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X); in LowerFROUND64()
2136 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in LowerFROUND64()
2137 const SDValue One = DAG.getConstant(1, SL, MVT::i32); in LowerFROUND64()
2138 const SDValue NegOne = DAG.getConstant(-1, SL, MVT::i32); in LowerFROUND64()
2139 const SDValue FiftyOne = DAG.getConstant(51, SL, MVT::i32); in LowerFROUND64()
2143 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X); in LowerFROUND64()
2145 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One); in LowerFROUND64()
2147 SDValue Exp = extractF64Exponent(Hi, SL, DAG); in LowerFROUND64()
2149 const SDValue Mask = DAG.getConstant(INT64_C(0x000fffffffffffff), SL, in LowerFROUND64()
2152 SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp); in LowerFROUND64()
2153 SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64, in LowerFROUND64()
2154 DAG.getConstant(INT64_C(0x0008000000000000), SL, in LowerFROUND64()
2158 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M); in LowerFROUND64()
2159 SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT, in LowerFROUND64()
2160 DAG.getConstant(0, SL, MVT::i64), Tmp0, in LowerFROUND64()
2163 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1, in LowerFROUND64()
2164 D, DAG.getConstant(0, SL, MVT::i64)); in LowerFROUND64()
2165 SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2); in LowerFROUND64()
2167 K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64)); in LowerFROUND64()
2168 K = DAG.getNode(ISD::BITCAST, SL, MVT::f64, K); in LowerFROUND64()
2170 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT); in LowerFROUND64()
2171 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT); in LowerFROUND64()
2172 SDValue ExpEqNegOne = DAG.getSetCC(SL, SetCCVT, NegOne, Exp, ISD::SETEQ); in LowerFROUND64()
2174 SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64, in LowerFROUND64()
2176 DAG.getConstantFP(1.0, SL, MVT::f64), in LowerFROUND64()
2177 DAG.getConstantFP(0.0, SL, MVT::f64)); in LowerFROUND64()
2179 SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X); in LowerFROUND64()
2181 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpLt0, S, K); in LowerFROUND64()
2182 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpGt51, X, K); in LowerFROUND64()
2200 SDLoc SL(Op); in LowerFFLOOR() local
2207 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFFLOOR()
2209 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64); in LowerFFLOOR()
2210 const SDValue NegOne = DAG.getConstantFP(-1.0, SL, MVT::f64); in LowerFFLOOR()
2215 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT); in LowerFFLOOR()
2216 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE); in LowerFFLOOR()
2217 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc); in LowerFFLOOR()
2219 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero); in LowerFFLOOR()
2221 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFFLOOR()
2228 SDLoc SL(Op); in LowerFLOG() local
2230 SDValue Log2Operand = DAG.getNode(ISD::FLOG2, SL, VT, Operand); in LowerFLOG()
2231 SDValue Log2BaseInvertedOperand = DAG.getConstantFP(Log2BaseInverted, SL, VT); in LowerFLOG()
2233 return DAG.getNode(ISD::FMUL, SL, VT, Log2Operand, Log2BaseInvertedOperand); in LowerFLOG()
2237 static SDValue getLog2EVal(SelectionDAG &DAG, const SDLoc &SL, EVT VT) { in getLog2EVal() argument
2240 return DAG.getConstantFP(1.44269504088896340735992468100189214f, SL, VT); in getLog2EVal()
2244 SL, VT); in getLog2EVal()
2247 APFloat(APFloat::IEEEdouble(), "0x1.71547652b82fep+0"), SL, VT); in getLog2EVal()
2256 SDLoc SL(Op); in lowerFEXP() local
2259 const SDValue K = getLog2EVal(DAG, SL, VT); in lowerFEXP()
2260 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Src, K, Op->getFlags()); in lowerFEXP()
2261 return DAG.getNode(ISD::FEXP2, SL, VT, Mul, Op->getFlags()); in lowerFEXP()
2273 SDLoc SL(Op); in LowerCTLZ_CTTZ() local
2290 return DAG.getNode(NewOpc, SL, MVT::i32, Src); in LowerCTLZ_CTTZ()
2292 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src); in LowerCTLZ_CTTZ()
2294 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in LowerCTLZ_CTTZ()
2295 const SDValue One = DAG.getConstant(1, SL, MVT::i32); in LowerCTLZ_CTTZ()
2297 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in LowerCTLZ_CTTZ()
2298 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in LowerCTLZ_CTTZ()
2304 SDValue Hi0orLo0 = DAG.getSetCC(SL, SetCCVT, HiOrLo, Zero, ISD::SETEQ); in LowerCTLZ_CTTZ()
2306 SDValue OprLo = DAG.getNode(ISDOpc, SL, MVT::i32, Lo); in LowerCTLZ_CTTZ()
2307 SDValue OprHi = DAG.getNode(ISDOpc, SL, MVT::i32, Hi); in LowerCTLZ_CTTZ()
2309 const SDValue Bits32 = DAG.getConstant(32, SL, MVT::i32); in LowerCTLZ_CTTZ()
2312 Add = DAG.getNode(ISD::ADD, SL, MVT::i32, OprLo, Bits32); in LowerCTLZ_CTTZ()
2314 NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32, Hi0orLo0, Add, OprHi); in LowerCTLZ_CTTZ()
2316 Add = DAG.getNode(ISD::ADD, SL, MVT::i32, OprHi, Bits32); in LowerCTLZ_CTTZ()
2318 NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32, Hi0orLo0, Add, OprLo); in LowerCTLZ_CTTZ()
2327 SDValue Lo0OrHi0 = DAG.getSetCC(SL, SetCCVT, LoOrHi, Zero, ISD::SETEQ); in LowerCTLZ_CTTZ()
2328 SDValue SrcIsZero = DAG.getNode(ISD::AND, SL, SetCCVT, Lo0OrHi0, Hi0orLo0); in LowerCTLZ_CTTZ()
2335 const SDValue Bits32 = DAG.getConstant(64, SL, MVT::i32); in LowerCTLZ_CTTZ()
2339 NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32, in LowerCTLZ_CTTZ()
2343 return DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i64, NewOpr); in LowerCTLZ_CTTZ()
2367 SDLoc SL(Op); in LowerINT_TO_FP32() local
2373 const SDValue SignBit = DAG.getConstant(63, SL, MVT::i64); in LowerINT_TO_FP32()
2374 S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit); in LowerINT_TO_FP32()
2376 SDValue LPlusS = DAG.getNode(ISD::ADD, SL, MVT::i64, L, S); in LowerINT_TO_FP32()
2377 L = DAG.getNode(ISD::XOR, SL, MVT::i64, LPlusS, S); in LowerINT_TO_FP32()
2384 SDValue ZeroI32 = DAG.getConstant(0, SL, MVT::i32); in LowerINT_TO_FP32()
2385 SDValue ZeroI64 = DAG.getConstant(0, SL, MVT::i64); in LowerINT_TO_FP32()
2386 SDValue LZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i64, L); in LowerINT_TO_FP32()
2387 LZ = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LZ); in LowerINT_TO_FP32()
2389 SDValue K = DAG.getConstant(127U + 63U, SL, MVT::i32); in LowerINT_TO_FP32()
2390 SDValue E = DAG.getSelect(SL, MVT::i32, in LowerINT_TO_FP32()
2391 DAG.getSetCC(SL, SetCCVT, L, ZeroI64, ISD::SETNE), in LowerINT_TO_FP32()
2392 DAG.getNode(ISD::SUB, SL, MVT::i32, K, LZ), in LowerINT_TO_FP32()
2395 SDValue U = DAG.getNode(ISD::AND, SL, MVT::i64, in LowerINT_TO_FP32()
2396 DAG.getNode(ISD::SHL, SL, MVT::i64, L, LZ), in LowerINT_TO_FP32()
2397 DAG.getConstant((-1ULL) >> 1, SL, MVT::i64)); in LowerINT_TO_FP32()
2399 SDValue T = DAG.getNode(ISD::AND, SL, MVT::i64, U, in LowerINT_TO_FP32()
2400 DAG.getConstant(0xffffffffffULL, SL, MVT::i64)); in LowerINT_TO_FP32()
2402 SDValue UShl = DAG.getNode(ISD::SRL, SL, MVT::i64, in LowerINT_TO_FP32()
2403 U, DAG.getConstant(40, SL, MVT::i64)); in LowerINT_TO_FP32()
2405 SDValue V = DAG.getNode(ISD::OR, SL, MVT::i32, in LowerINT_TO_FP32()
2406 DAG.getNode(ISD::SHL, SL, MVT::i32, E, DAG.getConstant(23, SL, MVT::i32)), in LowerINT_TO_FP32()
2407 DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, UShl)); in LowerINT_TO_FP32()
2409 SDValue C = DAG.getConstant(0x8000000000ULL, SL, MVT::i64); in LowerINT_TO_FP32()
2410 SDValue RCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETUGT); in LowerINT_TO_FP32()
2411 SDValue TCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETEQ); in LowerINT_TO_FP32()
2413 SDValue One = DAG.getConstant(1, SL, MVT::i32); in LowerINT_TO_FP32()
2415 SDValue VTrunc1 = DAG.getNode(ISD::AND, SL, MVT::i32, V, One); in LowerINT_TO_FP32()
2417 SDValue R = DAG.getSelect(SL, MVT::i32, in LowerINT_TO_FP32()
2420 DAG.getSelect(SL, MVT::i32, TCmp, VTrunc1, ZeroI32)); in LowerINT_TO_FP32()
2421 R = DAG.getNode(ISD::ADD, SL, MVT::i32, V, R); in LowerINT_TO_FP32()
2422 R = DAG.getNode(ISD::BITCAST, SL, MVT::f32, R); in LowerINT_TO_FP32()
2427 SDValue RNeg = DAG.getNode(ISD::FNEG, SL, MVT::f32, R); in LowerINT_TO_FP32()
2428 return DAG.getSelect(SL, MVT::f32, DAG.getSExtOrTrunc(S, SL, SetCCVT), RNeg, R); in LowerINT_TO_FP32()
2433 SDLoc SL(Op); in LowerINT_TO_FP64() local
2436 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src); in LowerINT_TO_FP64()
2438 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, in LowerINT_TO_FP64()
2439 DAG.getConstant(0, SL, MVT::i32)); in LowerINT_TO_FP64()
2440 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, in LowerINT_TO_FP64()
2441 DAG.getConstant(1, SL, MVT::i32)); in LowerINT_TO_FP64()
2444 SL, MVT::f64, Hi); in LowerINT_TO_FP64()
2446 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo); in LowerINT_TO_FP64()
2448 SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi, in LowerINT_TO_FP64()
2449 DAG.getConstant(32, SL, MVT::i32)); in LowerINT_TO_FP64()
2451 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo); in LowerINT_TO_FP64()
2510 SDLoc SL(Op); in LowerFP64_TO_INT() local
2514 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFP64_TO_INT()
2516 SDValue K0 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), SL, in LowerFP64_TO_INT()
2518 SDValue K1 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), SL, in LowerFP64_TO_INT()
2521 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0); in LowerFP64_TO_INT()
2523 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul); in LowerFP64_TO_INT()
2526 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc); in LowerFP64_TO_INT()
2528 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL, in LowerFP64_TO_INT()
2530 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma); in LowerFP64_TO_INT()
2532 SDValue Result = DAG.getBuildVector(MVT::v2i32, SL, {Lo, Hi}); in LowerFP64_TO_INT()
2534 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result); in LowerFP64_TO_INT()
2802 SDLoc SL(N); in performLoadCombine() local
2834 = DAG.getLoad(NewVT, SL, LN->getChain(), in performLoadCombine()
2837 SDValue BC = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad); in performLoadCombine()
2856 SDLoc SL(N); in performStoreCombine() local
2887 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NewVT, Val); in performStoreCombine()
2889 SDValue CastBack = DAG.getNode(ISD::BITCAST, SL, VT, CastVal); in performStoreCombine()
2893 return DAG.getStore(SN->getChain(), SL, CastVal, in performStoreCombine()
2910 SDLoc SL(N); in performAssertSZExtCombine() local
2915 SDValue NewInReg = DAG.getNode(N->getOpcode(), SL, SrcVT, Src, N1); in performAssertSZExtCombine()
2916 return DAG.getNode(ISD::TRUNCATE, SL, N->getValueType(0), NewInReg); in performAssertSZExtCombine()
2925 DAGCombinerInfo &DCI, const SDLoc &SL, in splitBinaryBitConstantOpImpl() argument
2932 SDValue LoRHS = DAG.getConstant(ValLo, SL, MVT::i32); in splitBinaryBitConstantOpImpl()
2933 SDValue HiRHS = DAG.getConstant(ValHi, SL, MVT::i32); in splitBinaryBitConstantOpImpl()
2935 SDValue LoAnd = DAG.getNode(Opc, SL, MVT::i32, Lo, LoRHS); in splitBinaryBitConstantOpImpl()
2936 SDValue HiAnd = DAG.getNode(Opc, SL, MVT::i32, Hi, HiRHS); in splitBinaryBitConstantOpImpl()
2943 SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {LoAnd, HiAnd}); in splitBinaryBitConstantOpImpl()
2944 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec); in splitBinaryBitConstantOpImpl()
2960 SDLoc SL(N); in performShlCombine() local
2975 SDValue Vec = DAG.getBuildVector(MVT::v2i16, SL, in performShlCombine()
2976 { DAG.getConstant(0, SL, MVT::i16), LHS->getOperand(0) }); in performShlCombine()
2977 return DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec); in performShlCombine()
2988 SDValue Shl = DAG.getNode(ISD::SHL, SL, XVT, X, SDValue(RHS, 0)); in performShlCombine()
2989 return DAG.getZExtOrTrunc(Shl, SL, VT); in performShlCombine()
3004 SDValue ShiftAmt = DAG.getConstant(RHSVal - 32, SL, MVT::i32); in performShlCombine()
3006 SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS); in performShlCombine()
3007 SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, ShiftAmt); in performShlCombine()
3009 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in performShlCombine()
3011 SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {Zero, NewShift}); in performShlCombine()
3012 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec); in performShlCombine()
3025 SDLoc SL(N); in performSraCombine() local
3031 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine()
3032 DAG.getConstant(31, SL, MVT::i32)); in performSraCombine()
3034 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {Hi, NewShift}); in performSraCombine()
3035 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec); in performSraCombine()
3041 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine()
3042 DAG.getConstant(31, SL, MVT::i32)); in performSraCombine()
3043 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, NewShift}); in performSraCombine()
3044 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec); in performSraCombine()
3068 SDLoc SL(N); in performSrlCombine() local
3070 SDValue One = DAG.getConstant(1, SL, MVT::i32); in performSrlCombine()
3071 SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in performSrlCombine()
3073 SDValue VecOp = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, N->getOperand(0)); in performSrlCombine()
3074 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, in performSrlCombine()
3077 SDValue NewConst = DAG.getConstant(ShiftAmt - 32, SL, MVT::i32); in performSrlCombine()
3078 SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst); in performSrlCombine()
3080 SDValue BuildPair = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, Zero}); in performSrlCombine()
3082 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildPair); in performSrlCombine()
3087 SDLoc SL(N); in performTruncateCombine() local
3100 Elt0 = DAG.getNode(ISD::BITCAST, SL, in performTruncateCombine()
3104 return DAG.getNode(ISD::TRUNCATE, SL, VT, Elt0); in performTruncateCombine()
3121 SrcElt = DAG.getNode(ISD::BITCAST, SL, in performTruncateCombine()
3125 return DAG.getNode(ISD::TRUNCATE, SL, VT, SrcElt); in performTruncateCombine()
3151 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MidVT, in performTruncateCombine()
3156 Amt = DAG.getZExtOrTrunc(Amt, SL, NewShiftVT); in performTruncateCombine()
3160 SDValue ShrunkShift = DAG.getNode(Src.getOpcode(), SL, MidVT, in performTruncateCombine()
3162 return DAG.getNode(ISD::TRUNCATE, SL, VT, ShrunkShift); in performTruncateCombine()
3174 static SDValue getMul24(SelectionDAG &DAG, const SDLoc &SL, in getMul24() argument
3178 return DAG.getNode(MulOpc, SL, MVT::i32, N0, N1); in getMul24()
3187 SDValue Mul = DAG.getNode(MulOpc, SL, in getMul24()
3190 return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64, in getMul24()
3305 SDLoc SL(N); in performMulLoHi24Combine() local
3307 SDValue MulLo = DAG.getNode(MulLoOpc, SL, MVT::i32, N0, N1); in performMulLoHi24Combine()
3308 SDValue MulHi = DAG.getNode(MulHiOpc, SL, MVT::i32, N0, N1); in performMulLoHi24Combine()
3309 return DAG.getMergeValues({ MulLo, MulHi }, SL); in performMulLoHi24Combine()
3345 SDValue AMDGPUTargetLowering::performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, in performCtlz_CttzCombine() argument
3365 return getFFBX_U32(DAG, CmpLHS, SL, Opc); in performCtlz_CttzCombine()
3374 return getFFBX_U32(DAG, CmpLHS, SL, Opc); in performCtlz_CttzCombine()
3382 const SDLoc &SL, in distributeOpThroughSelect() argument
3389 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT, Cond, in distributeOpThroughSelect()
3392 return DAG.getNode(Op, SL, VT, NewSelect); in distributeOpThroughSelect()
3425 SDLoc SL(N); in foldFreeOpFromSelect() local
3444 NewRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in foldFreeOpFromSelect()
3451 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT, in foldFreeOpFromSelect()
3454 return DAG.getNode(LHS.getOpcode(), SL, VT, NewSelect); in foldFreeOpFromSelect()
3489 SDLoc SL(N); in performSelectCombine() local
3493 SDValue NewCond = DAG.getSetCC(SL, Cond.getValueType(), LHS, RHS, NewCC); in performSelectCombine()
3494 return DAG.getNode(ISD::SELECT, SL, VT, NewCond, False, True); in performSelectCombine()
3576 SDLoc SL(N); in performFNegCombine() local
3587 LHS = DAG.getNode(ISD::FNEG, SL, VT, LHS); in performFNegCombine()
3592 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
3596 SDValue Res = DAG.getNode(ISD::FADD, SL, VT, LHS, RHS, N0->getFlags()); in performFNegCombine()
3598 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
3613 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
3615 SDValue Res = DAG.getNode(Opc, SL, VT, LHS, RHS, N0->getFlags()); in performFNegCombine()
3617 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
3635 MHS = DAG.getNode(ISD::FNEG, SL, VT, MHS); in performFNegCombine()
3638 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
3642 SDValue Res = DAG.getNode(Opc, SL, VT, LHS, MHS, RHS); in performFNegCombine()
3644 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
3666 SDValue NegLHS = DAG.getNode(ISD::FNEG, SL, VT, LHS); in performFNegCombine()
3667 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
3670 SDValue Res = DAG.getNode(Opposite, SL, VT, NegLHS, NegRHS, N0->getFlags()); in performFNegCombine()
3672 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
3678 Ops[I] = DAG.getNode(ISD::FNEG, SL, VT, N0->getOperand(I), N0->getFlags()); in performFNegCombine()
3680 SDValue Res = DAG.getNode(AMDGPUISD::FMED3, SL, VT, Ops, N0->getFlags()); in performFNegCombine()
3682 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
3699 return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0)); in performFNegCombine()
3707 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
3708 return DAG.getNode(Opc, SL, VT, Neg, N0->getFlags()); in performFNegCombine()
3715 return DAG.getNode(ISD::FP_ROUND, SL, VT, in performFNegCombine()
3723 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
3724 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1)); in performFNegCombine()
3730 SDLoc SL(N); in performFNegCombine() local
3736 SDValue IntFNeg = DAG.getNode(ISD::XOR, SL, SrcVT, Src, in performFNegCombine()
3737 DAG.getConstant(0x8000, SL, SrcVT)); in performFNegCombine()
3738 return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFNeg); in performFNegCombine()
3756 SDLoc SL(N); in performFAbsCombine() local
3761 SDValue IntFAbs = DAG.getNode(ISD::AND, SL, SrcVT, Src, in performFAbsCombine()
3762 DAG.getConstant(0x7fff, SL, SrcVT)); in performFAbsCombine()
3763 return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFAbs); in performFAbsCombine()
3808 SDLoc SL(N); in PerformDAGCombine() local
3814 return DAG.getBuildVector(DestVT, SL, CastedElts); in PerformDAGCombine()
3829 SDLoc SL(N); in PerformDAGCombine() local
3831 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, in PerformDAGCombine()
3832 DAG.getConstant(Lo_32(CVal), SL, MVT::i32), in PerformDAGCombine()
3833 DAG.getConstant(Hi_32(CVal), SL, MVT::i32)); in PerformDAGCombine()
3834 return DAG.getNode(ISD::BITCAST, SL, DestVT, BV); in PerformDAGCombine()
3840 SDLoc SL(N); in PerformDAGCombine() local
3842 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, in PerformDAGCombine()
3843 DAG.getConstant(Lo_32(CVal), SL, MVT::i32), in PerformDAGCombine()
3844 DAG.getConstant(Hi_32(CVal), SL, MVT::i32)); in PerformDAGCombine()
3846 return DAG.getNode(ISD::BITCAST, SL, DestVT, Vec); in PerformDAGCombine()
3999 const SDLoc &SL, in CreateLiveInRegister() argument
4015 return DAG.getCopyFromReg(DAG.getEntryNode(), SL, VReg, VT); in CreateLiveInRegister()
4020 const SDLoc &SL, in loadStackInputValue() argument
4029 return DAG.getLoad(VT, SL, DAG.getEntryNode(), Ptr, SrcPtrInfo, 4, in loadStackInputValue()
4035 const SDLoc &SL, in storeStackInputValue() argument
4042 SDValue Ptr = DAG.getConstant(Offset, SL, MVT::i32); in storeStackInputValue()
4043 SDValue Store = DAG.getStore(Chain, SL, ArgVal, Ptr, DstInfo, 4, in storeStackInputValue()
4050 EVT VT, const SDLoc &SL, in loadInputValue() argument
4055 return CreateLiveInRegister(DAG, RC, Arg.getRegister(), VT, SL); in loadInputValue()
4056 return loadStackInputValue(DAG, VT, SL, Arg.getStackOffset()); in loadInputValue()