Lines Matching refs:DestVT
835 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const { in isNarrowingProfitable()
842 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32; in isNarrowingProfitable()
2461 EVT DestVT = Op.getValueType(); in LowerUINT_TO_FP() local
2462 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) { in LowerUINT_TO_FP()
2474 if (DestVT == MVT::f32) in LowerUINT_TO_FP()
2477 assert(DestVT == MVT::f64); in LowerUINT_TO_FP()
2488 EVT DestVT = Op.getValueType(); in LowerSINT_TO_FP() local
2489 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) { in LowerSINT_TO_FP()
2501 if (DestVT == MVT::f32) in LowerSINT_TO_FP()
2504 assert(DestVT == MVT::f64); in LowerSINT_TO_FP()
3791 EVT DestVT = N->getValueType(0); in PerformDAGCombine() local
3798 if (DestVT.isVector()) { in PerformDAGCombine()
3802 unsigned NElts = DestVT.getVectorNumElements(); in PerformDAGCombine()
3805 EVT DestEltVT = DestVT.getVectorElementType(); in PerformDAGCombine()
3814 return DAG.getBuildVector(DestVT, SL, CastedElts); in PerformDAGCombine()
3819 if (DestVT.getSizeInBits() != 64 && !DestVT.isVector()) in PerformDAGCombine()
3834 return DAG.getNode(ISD::BITCAST, SL, DestVT, BV); in PerformDAGCombine()
3846 return DAG.getNode(ISD::BITCAST, SL, DestVT, Vec); in PerformDAGCombine()