121 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {  in getEquivalentMemType()
130 unsigned AMDGPUTargetLowering::numBitsUnsigned(SDValue Op, SelectionDAG &DAG) {  in numBitsUnsigned()
136 unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) {  in numBitsSigned()
144 AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,  in AMDGPUTargetLowering()  function in AMDGPUTargetLowering
609 bool AMDGPUTargetLowering::allUsesHaveSourceMods(const SDNode *N,  in allUsesHaveSourceMods()
633 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {  in getVectorIdxTy()
637 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {  in isSelectSupported()
643 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {  in isFPImmLegal()
650 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {  in ShouldShrinkFPConstant()
655 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,  in shouldReduceLoadWidth()
693 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,  in isLoadBitCastBeneficial()
712 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {  in isCheapToSpeculateCttz()
716 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {  in isCheapToSpeculateCtlz()
720 bool AMDGPUTargetLowering::isSDNodeAlwaysUniform(const SDNode * N) const {  in isSDNodeAlwaysUniform()
755 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {  in isFAbsFree()
763 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {  in isFNegFree()
770 bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(EVT MemVT,  in storeOfVectorConstantIsCheap()
776 bool AMDGPUTargetLowering::aggressivelyPreferBuildVectorSources(EVT VecVT) const {  in aggressivelyPreferBuildVectorSources()
788 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {  in isTruncateFree()
797 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {  in isTruncateFree()
809 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {  in isZExtFree()
819 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {  in isZExtFree()
831 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {  in isZExtFree()
835 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {  in isNarrowingProfitable()
921 void AMDGPUTargetLowering::analyzeFormalArgumentsCompute(  in analyzeFormalArgumentsCompute()
1031 SDValue AMDGPUTargetLowering::LowerReturn(  in LowerReturn()
1048 CCAssignFn *AMDGPUTargetLowering::CCAssignFnForCall(CallingConv::ID CC,  in CCAssignFnForCall()
1053 CCAssignFn *AMDGPUTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,  in CCAssignFnForReturn()
1058 SDValue AMDGPUTargetLowering::addTokenForArgument(SDValue Chain,  in addTokenForArgument()
1094 SDValue AMDGPUTargetLowering::lowerUnhandledCall(CallLoweringInfo &CLI,  in lowerUnhandledCall()
1121 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,  in LowerCall()
1126 SDValue AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,  in LowerDYNAMIC_STACKALLOC()
1137 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,  in LowerOperation()
1178 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,  in ReplaceNodeResults()
1203 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,  in LowerGlobalAddress()
1238 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,  in LowerCONCAT_VECTORS()
1258 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,  in LowerEXTRACT_SUBVECTOR()
1271 SDValue AMDGPUTargetLowering::combineFMinMaxLegacy(const SDLoc &DL, EVT VT,  in combineFMinMaxLegacy()
1345 AMDGPUTargetLowering::split64BitValue(SDValue Op, SelectionDAG &DAG) const {  in split64BitValue()
1359 SDValue AMDGPUTargetLowering::getLoHalf64(SDValue Op, SelectionDAG &DAG) const {  in getLoHalf64()
1367 SDValue AMDGPUTargetLowering::getHiHalf64(SDValue Op, SelectionDAG &DAG) const {  in getHiHalf64()
1375 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,  in SplitVectorLoad()
1422 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,  in SplitVectorStore()
1466 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG,  in LowerDIVREM24()
1572 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,  in LowerUDIVREM64()
1782 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,  in LowerUDIVREM()
1897 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,  in LowerSDIVREM()
1958 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {  in LowerFREM()
1973 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {  in LowerFCEIL()
2013 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {  in LowerFTRUNC()
2062 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {  in LowerFRINT()
2089 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {  in LowerFNEARBYINT()
2101 SDValue AMDGPUTargetLowering::LowerFROUND32_16(SDValue Op, SelectionDAG &DAG) const {  in LowerFROUND32_16()
2130 SDValue AMDGPUTargetLowering::LowerFROUND64(SDValue Op, SelectionDAG &DAG) const {  in LowerFROUND64()
2187 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {  in LowerFROUND()
2199 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {  in LowerFFLOOR()
2224 SDValue AMDGPUTargetLowering::LowerFLOG(SDValue Op, SelectionDAG &DAG,  in LowerFLOG()
2254 SDValue AMDGPUTargetLowering::lowerFEXP(SDValue Op, SelectionDAG &DAG) const {  in lowerFEXP()
2272 SDValue AMDGPUTargetLowering::LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const {  in LowerCTLZ_CTTZ()
2346 SDValue AMDGPUTargetLowering::LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG,  in LowerINT_TO_FP32()
2431 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,  in LowerINT_TO_FP64()
2454 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,  in LowerUINT_TO_FP()
2481 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,  in LowerSINT_TO_FP()
2508 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,  in LowerFP64_TO_INT()
2537 SDValue AMDGPUTargetLowering::LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const {  in LowerFP_TO_FP16()
2636 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,  in LowerFP_TO_SINT()
2659 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,  in LowerFP_TO_UINT()
2682 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,  in LowerSIGN_EXTEND_INREG()
2710   return AMDGPUTargetLowering::numBitsUnsigned(Op, DAG) <= 24;  in isU24()
2717     AMDGPUTargetLowering::numBitsSigned(Op, DAG) < 24;  in isI24()
2772 bool AMDGPUTargetLowering::shouldCombineMemoryType(EVT VT) const {  in shouldCombineMemoryType()
2793 SDValue AMDGPUTargetLowering::performLoadCombine(SDNode *N,  in performLoadCombine()
2844 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,  in performStoreCombine()
2900 SDValue AMDGPUTargetLowering::performAssertSZExtCombine(SDNode *N,  in performAssertSZExtCombine()
2924 SDValue AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(  in splitBinaryBitConstantOpImpl()
2947 SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,  in performShlCombine()
3015 SDValue AMDGPUTargetLowering::performSraCombine(SDNode *N,  in performSraCombine()
3050 SDValue AMDGPUTargetLowering::performSrlCombine(SDNode *N,  in performSrlCombine()
3085 SDValue AMDGPUTargetLowering::performTruncateCombine(  in performTruncateCombine()
3194 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,  in performMulCombine()
3241 SDValue AMDGPUTargetLowering::performMulhsCombine(SDNode *N,  in performMulhsCombine()
3265 SDValue AMDGPUTargetLowering::performMulhuCombine(SDNode *N,  in performMulhuCombine()
3289 SDValue AMDGPUTargetLowering::performMulLoHi24Combine(  in performMulLoHi24Combine()
3318 SDValue AMDGPUTargetLowering::getFFBX_U32(SelectionDAG &DAG,  in getFFBX_U32()
3345 SDValue AMDGPUTargetLowering::performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond,  in performCtlz_CttzCombine()
3462 SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,  in performSelectCombine()
3522 bool AMDGPUTargetLowering::isConstantCostlierToNegate(SDValue N) const {  in isConstantCostlierToNegate()
3553 SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,  in performFNegCombine()
3745 SDValue AMDGPUTargetLowering::performFAbsCombine(SDNode *N,  in performFAbsCombine()
3770 SDValue AMDGPUTargetLowering::performRcpCombine(SDNode *N,  in performRcpCombine()
3782 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,  in PerformDAGCombine()
3996 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,  in CreateLiveInRegister()
4018 SDValue AMDGPUTargetLowering::loadStackInputValue(SelectionDAG &DAG,  in loadStackInputValue()
4034 SDValue AMDGPUTargetLowering::storeStackInputValue(SelectionDAG &DAG,  in storeStackInputValue()
4048 SDValue AMDGPUTargetLowering::loadInputValue(SelectionDAG &DAG,  in loadInputValue()
4059 uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(  in getImplicitParameterOffset()
4079 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {  in getTargetNodeName()
4226 SDValue AMDGPUTargetLowering::getSqrtEstimate(SDValue Operand,  in getSqrtEstimate()
4244 SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,  in getRecipEstimate()
4265 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(  in computeKnownBitsForTargetNode()
4390 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(  in ComputeNumSignBitsForTargetNode()
4424 bool AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,  in isKnownNeverNaNForTargetNode()
4522 AMDGPUTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {  in shouldExpandAtomicRMWInIR()