Lines Matching refs:getShiftExtendAmount

610   unsigned getShiftExtendAmount() const {  in getShiftExtendAmount()  function in __anon7d8c15f70111::AArch64Operand
1112 bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8); in isSVEDataVectorRegWithShiftExtend()
1170 getShiftExtendAmount() == Log2_32(ExtWidth / 8)) in isGPR64WithShiftExtend()
1269 getShiftExtendAmount() <= 4; in isExtend()
1286 getShiftExtendAmount() <= 4; in isExtendLSL64()
1294 (getShiftExtendAmount() == Log2_32(Width / 8) || in isMemXExtend()
1295 getShiftExtendAmount() == 0); in isMemXExtend()
1303 (getShiftExtendAmount() == Log2_32(Width / 8) || in isMemWExtend()
1304 getShiftExtendAmount() == 0); in isMemWExtend()
1315 ST == AArch64_AM::ASR) && getShiftExtendAmount() < width; in isArithmeticShifter()
1327 getShiftExtendAmount() < width; in isLogicalShifter()
1338 uint64_t Val = getShiftExtendAmount(); in isMovImm32Shifter()
1350 uint64_t Val = getShiftExtendAmount(); in isMovImm64Shifter()
1359 unsigned Shift = getShiftExtendAmount(); in isLogicalVecShifter()
1369 unsigned Shift = getShiftExtendAmount(); in isLogicalVecHalfWordShifter()
1379 unsigned Shift = getShiftExtendAmount(); in isMoveVecShifter()
1741 AArch64_AM::getShifterImm(getShiftExtendType(), getShiftExtendAmount()); in addShifterOperands()
1749 unsigned Imm = AArch64_AM::getArithExtendImm(ET, getShiftExtendAmount()); in addExtendOperands()
1757 unsigned Imm = AArch64_AM::getArithExtendImm(ET, getShiftExtendAmount()); in addExtend64Operands()
1766 Inst.addOperand(MCOperand::createImm(getShiftExtendAmount() != 0)); in addMemExtendOperands()
2076 if (!getShiftExtendAmount() && !hasShiftExtendAmount()) in print()
2084 << getShiftExtendAmount(); in print()
3494 Ext->getShiftExtendType(), Ext->getShiftExtendAmount(), in tryParseGPROperand()
5710 getContext(), Ext->getShiftExtendType(), Ext->getShiftExtendAmount(), in tryParseSVEDataVector()